1/* 2 * drivers/usb/musb/ux500_dma.c 3 * 4 * U8500 DMA support code 5 * 6 * Copyright (C) 2009 STMicroelectronics 7 * Copyright (C) 2011 ST-Ericsson SA 8 * Authors: 9 * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> 10 * Praveena Nadahally <praveen.nadahally@stericsson.com> 11 * Rajaram Regupathy <ragupathy.rajaram@stericsson.com> 12 * 13 * This program is free software: you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation, either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program. If not, see <http://www.gnu.org/licenses/>. 25 */ 26 27#include <linux/device.h> 28#include <linux/interrupt.h> 29#include <linux/platform_device.h> 30#include <linux/dma-mapping.h> 31#include <linux/dmaengine.h> 32#include <linux/pfn.h> 33#include <linux/sizes.h> 34#include <linux/platform_data/usb-musb-ux500.h> 35#include "musb_core.h" 36 37static const char *iep_chan_names[] = { "iep_1_9", "iep_2_10", "iep_3_11", "iep_4_12", 38 "iep_5_13", "iep_6_14", "iep_7_15", "iep_8" }; 39static const char *oep_chan_names[] = { "oep_1_9", "oep_2_10", "oep_3_11", "oep_4_12", 40 "oep_5_13", "oep_6_14", "oep_7_15", "oep_8" }; 41 42struct ux500_dma_channel { 43 struct dma_channel channel; 44 struct ux500_dma_controller *controller; 45 struct musb_hw_ep *hw_ep; 46 struct dma_chan *dma_chan; 47 unsigned int cur_len; 48 dma_cookie_t cookie; 49 u8 ch_num; 50 u8 is_tx; 51 u8 is_allocated; 52}; 53 54struct ux500_dma_controller { 55 struct dma_controller controller; 56 struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]; 57 struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]; 58 void *private_data; 59 dma_addr_t phy_base; 60}; 61 62/* Work function invoked from DMA callback to handle rx transfers. */ 63static void ux500_dma_callback(void *private_data) 64{ 65 struct dma_channel *channel = private_data; 66 struct ux500_dma_channel *ux500_channel = channel->private_data; 67 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; 68 struct musb *musb = hw_ep->musb; 69 unsigned long flags; 70 71 dev_dbg(musb->controller, "DMA rx transfer done on hw_ep=%d\n", 72 hw_ep->epnum); 73 74 spin_lock_irqsave(&musb->lock, flags); 75 ux500_channel->channel.actual_len = ux500_channel->cur_len; 76 ux500_channel->channel.status = MUSB_DMA_STATUS_FREE; 77 musb_dma_completion(musb, hw_ep->epnum, ux500_channel->is_tx); 78 spin_unlock_irqrestore(&musb->lock, flags); 79 80} 81 82static bool ux500_configure_channel(struct dma_channel *channel, 83 u16 packet_sz, u8 mode, 84 dma_addr_t dma_addr, u32 len) 85{ 86 struct ux500_dma_channel *ux500_channel = channel->private_data; 87 struct musb_hw_ep *hw_ep = ux500_channel->hw_ep; 88 struct dma_chan *dma_chan = ux500_channel->dma_chan; 89 struct dma_async_tx_descriptor *dma_desc; 90 enum dma_transfer_direction direction; 91 struct scatterlist sg; 92 struct dma_slave_config slave_conf; 93 enum dma_slave_buswidth addr_width; 94 dma_addr_t usb_fifo_addr = (MUSB_FIFO_OFFSET(hw_ep->epnum) + 95 ux500_channel->controller->phy_base); 96 struct musb *musb = ux500_channel->controller->private_data; 97 98 dev_dbg(musb->controller, 99 "packet_sz=%d, mode=%d, dma_addr=0x%llx, len=%d is_tx=%d\n", 100 packet_sz, mode, (unsigned long long) dma_addr, 101 len, ux500_channel->is_tx); 102 103 ux500_channel->cur_len = len; 104 105 sg_init_table(&sg, 1); 106 sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len, 107 offset_in_page(dma_addr)); 108 sg_dma_address(&sg) = dma_addr; 109 sg_dma_len(&sg) = len; 110 111 direction = ux500_channel->is_tx ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 112 addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE : 113 DMA_SLAVE_BUSWIDTH_4_BYTES; 114 115 slave_conf.direction = direction; 116 slave_conf.src_addr = usb_fifo_addr; 117 slave_conf.src_addr_width = addr_width; 118 slave_conf.src_maxburst = 16; 119 slave_conf.dst_addr = usb_fifo_addr; 120 slave_conf.dst_addr_width = addr_width; 121 slave_conf.dst_maxburst = 16; 122 slave_conf.device_fc = false; 123 124 dma_chan->device->device_control(dma_chan, DMA_SLAVE_CONFIG, 125 (unsigned long) &slave_conf); 126 127 dma_desc = dmaengine_prep_slave_sg(dma_chan, &sg, 1, direction, 128 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 129 if (!dma_desc) 130 return false; 131 132 dma_desc->callback = ux500_dma_callback; 133 dma_desc->callback_param = channel; 134 ux500_channel->cookie = dma_desc->tx_submit(dma_desc); 135 136 dma_async_issue_pending(dma_chan); 137 138 return true; 139} 140 141static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c, 142 struct musb_hw_ep *hw_ep, u8 is_tx) 143{ 144 struct ux500_dma_controller *controller = container_of(c, 145 struct ux500_dma_controller, controller); 146 struct ux500_dma_channel *ux500_channel = NULL; 147 struct musb *musb = controller->private_data; 148 u8 ch_num = hw_ep->epnum - 1; 149 150 /* 8 DMA channels (0 - 7). Each DMA channel can only be allocated 151 * to specified hw_ep. For example DMA channel 0 can only be allocated 152 * to hw_ep 1 and 9. 153 */ 154 if (ch_num > 7) 155 ch_num -= 8; 156 157 if (ch_num >= UX500_MUSB_DMA_NUM_RX_TX_CHANNELS) 158 return NULL; 159 160 ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) : 161 &(controller->rx_channel[ch_num]) ; 162 163 /* Check if channel is already used. */ 164 if (ux500_channel->is_allocated) 165 return NULL; 166 167 ux500_channel->hw_ep = hw_ep; 168 ux500_channel->is_allocated = 1; 169 170 dev_dbg(musb->controller, "hw_ep=%d, is_tx=0x%x, channel=%d\n", 171 hw_ep->epnum, is_tx, ch_num); 172 173 return &(ux500_channel->channel); 174} 175 176static void ux500_dma_channel_release(struct dma_channel *channel) 177{ 178 struct ux500_dma_channel *ux500_channel = channel->private_data; 179 struct musb *musb = ux500_channel->controller->private_data; 180 181 dev_dbg(musb->controller, "channel=%d\n", ux500_channel->ch_num); 182 183 if (ux500_channel->is_allocated) { 184 ux500_channel->is_allocated = 0; 185 channel->status = MUSB_DMA_STATUS_FREE; 186 channel->actual_len = 0; 187 } 188} 189 190static int ux500_dma_is_compatible(struct dma_channel *channel, 191 u16 maxpacket, void *buf, u32 length) 192{ 193 if ((maxpacket & 0x3) || 194 ((unsigned long int) buf & 0x3) || 195 (length < 512) || 196 (length & 0x3)) 197 return false; 198 else 199 return true; 200} 201 202static int ux500_dma_channel_program(struct dma_channel *channel, 203 u16 packet_sz, u8 mode, 204 dma_addr_t dma_addr, u32 len) 205{ 206 int ret; 207 208 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 209 channel->status == MUSB_DMA_STATUS_BUSY); 210 211 if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len)) 212 return false; 213 214 channel->status = MUSB_DMA_STATUS_BUSY; 215 channel->actual_len = 0; 216 ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len); 217 if (!ret) 218 channel->status = MUSB_DMA_STATUS_FREE; 219 220 return ret; 221} 222 223static int ux500_dma_channel_abort(struct dma_channel *channel) 224{ 225 struct ux500_dma_channel *ux500_channel = channel->private_data; 226 struct ux500_dma_controller *controller = ux500_channel->controller; 227 struct musb *musb = controller->private_data; 228 void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs; 229 u16 csr; 230 231 dev_dbg(musb->controller, "channel=%d, is_tx=%d\n", 232 ux500_channel->ch_num, ux500_channel->is_tx); 233 234 if (channel->status == MUSB_DMA_STATUS_BUSY) { 235 if (ux500_channel->is_tx) { 236 csr = musb_readw(epio, MUSB_TXCSR); 237 csr &= ~(MUSB_TXCSR_AUTOSET | 238 MUSB_TXCSR_DMAENAB | 239 MUSB_TXCSR_DMAMODE); 240 musb_writew(epio, MUSB_TXCSR, csr); 241 } else { 242 csr = musb_readw(epio, MUSB_RXCSR); 243 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 244 MUSB_RXCSR_DMAENAB | 245 MUSB_RXCSR_DMAMODE); 246 musb_writew(epio, MUSB_RXCSR, csr); 247 } 248 249 ux500_channel->dma_chan->device-> 250 device_control(ux500_channel->dma_chan, 251 DMA_TERMINATE_ALL, 0); 252 channel->status = MUSB_DMA_STATUS_FREE; 253 } 254 return 0; 255} 256 257static void ux500_dma_controller_stop(struct ux500_dma_controller *controller) 258{ 259 struct ux500_dma_channel *ux500_channel; 260 struct dma_channel *channel; 261 u8 ch_num; 262 263 for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) { 264 channel = &controller->rx_channel[ch_num].channel; 265 ux500_channel = channel->private_data; 266 267 ux500_dma_channel_release(channel); 268 269 if (ux500_channel->dma_chan) 270 dma_release_channel(ux500_channel->dma_chan); 271 } 272 273 for (ch_num = 0; ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; ch_num++) { 274 channel = &controller->tx_channel[ch_num].channel; 275 ux500_channel = channel->private_data; 276 277 ux500_dma_channel_release(channel); 278 279 if (ux500_channel->dma_chan) 280 dma_release_channel(ux500_channel->dma_chan); 281 } 282} 283 284static int ux500_dma_controller_start(struct ux500_dma_controller *controller) 285{ 286 struct ux500_dma_channel *ux500_channel = NULL; 287 struct musb *musb = controller->private_data; 288 struct device *dev = musb->controller; 289 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev); 290 struct ux500_musb_board_data *data; 291 struct dma_channel *dma_channel = NULL; 292 char **chan_names; 293 u32 ch_num; 294 u8 dir; 295 u8 is_tx = 0; 296 297 void **param_array; 298 struct ux500_dma_channel *channel_array; 299 dma_cap_mask_t mask; 300 301 if (!plat) { 302 dev_err(musb->controller, "No platform data\n"); 303 return -EINVAL; 304 } 305 306 data = plat->board_data; 307 308 dma_cap_zero(mask); 309 dma_cap_set(DMA_SLAVE, mask); 310 311 /* Prepare the loop for RX channels */ 312 channel_array = controller->rx_channel; 313 param_array = data ? data->dma_rx_param_array : NULL; 314 chan_names = (char **)iep_chan_names; 315 316 for (dir = 0; dir < 2; dir++) { 317 for (ch_num = 0; 318 ch_num < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; 319 ch_num++) { 320 ux500_channel = &channel_array[ch_num]; 321 ux500_channel->controller = controller; 322 ux500_channel->ch_num = ch_num; 323 ux500_channel->is_tx = is_tx; 324 325 dma_channel = &(ux500_channel->channel); 326 dma_channel->private_data = ux500_channel; 327 dma_channel->status = MUSB_DMA_STATUS_FREE; 328 dma_channel->max_len = SZ_16M; 329 330 ux500_channel->dma_chan = 331 dma_request_slave_channel(dev, chan_names[ch_num]); 332 333 if (!ux500_channel->dma_chan) 334 ux500_channel->dma_chan = 335 dma_request_channel(mask, 336 data ? 337 data->dma_filter : 338 NULL, 339 param_array ? 340 param_array[ch_num] : 341 NULL); 342 343 if (!ux500_channel->dma_chan) { 344 ERR("Dma pipe allocation error dir=%d ch=%d\n", 345 dir, ch_num); 346 347 /* Release already allocated channels */ 348 ux500_dma_controller_stop(controller); 349 350 return -EBUSY; 351 } 352 353 } 354 355 /* Prepare the loop for TX channels */ 356 channel_array = controller->tx_channel; 357 param_array = data ? data->dma_tx_param_array : NULL; 358 chan_names = (char **)oep_chan_names; 359 is_tx = 1; 360 } 361 362 return 0; 363} 364 365void dma_controller_destroy(struct dma_controller *c) 366{ 367 struct ux500_dma_controller *controller = container_of(c, 368 struct ux500_dma_controller, controller); 369 370 ux500_dma_controller_stop(controller); 371 kfree(controller); 372} 373 374struct dma_controller *dma_controller_create(struct musb *musb, 375 void __iomem *base) 376{ 377 struct ux500_dma_controller *controller; 378 struct platform_device *pdev = to_platform_device(musb->controller); 379 struct resource *iomem; 380 int ret; 381 382 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 383 if (!controller) 384 goto kzalloc_fail; 385 386 controller->private_data = musb; 387 388 /* Save physical address for DMA controller. */ 389 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 390 if (!iomem) { 391 dev_err(musb->controller, "no memory resource defined\n"); 392 goto plat_get_fail; 393 } 394 395 controller->phy_base = (dma_addr_t) iomem->start; 396 397 controller->controller.channel_alloc = ux500_dma_channel_allocate; 398 controller->controller.channel_release = ux500_dma_channel_release; 399 controller->controller.channel_program = ux500_dma_channel_program; 400 controller->controller.channel_abort = ux500_dma_channel_abort; 401 controller->controller.is_compatible = ux500_dma_is_compatible; 402 403 ret = ux500_dma_controller_start(controller); 404 if (ret) 405 goto plat_get_fail; 406 return &controller->controller; 407 408plat_get_fail: 409 kfree(controller); 410kzalloc_fail: 411 return NULL; 412} 413