common.h revision 4bd0481152d0d5e8326d7e24329b0069713ed718 
1/*
2 * Renesas USB driver
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
15 *
16 */
17#ifndef RENESAS_USB_DRIVER_H
18#define RENESAS_USB_DRIVER_H
19
20#include <linux/platform_device.h>
21#include <linux/usb/renesas_usbhs.h>
22
23struct usbhs_priv;
24
25#include "./mod.h"
26#include "./pipe.h"
27
28/*
29 *
30 *		register define
31 *
32 */
33#define SYSCFG		0x0000
34#define BUSWAIT		0x0002
35#define DVSTCTR		0x0008
36#define CFIFO		0x0014
37#define CFIFOSEL	0x0020
38#define CFIFOCTR	0x0022
39#define INTENB0		0x0030
40#define INTENB1		0x0032
41#define BRDYENB		0x0036
42#define NRDYENB		0x0038
43#define BEMPENB		0x003A
44#define INTSTS0		0x0040
45#define INTSTS1		0x0042
46#define BRDYSTS		0x0046
47#define NRDYSTS		0x0048
48#define BEMPSTS		0x004A
49#define FRMNUM		0x004C
50#define USBREQ		0x0054	/* USB request type register */
51#define USBVAL		0x0056	/* USB request value register */
52#define USBINDX		0x0058	/* USB request index register */
53#define USBLENG		0x005A	/* USB request length register */
54#define DCPCFG		0x005C
55#define DCPMAXP		0x005E
56#define DCPCTR		0x0060
57#define PIPESEL		0x0064
58#define PIPECFG		0x0068
59#define PIPEBUF		0x006A
60#define PIPEMAXP	0x006C
61#define PIPEPERI	0x006E
62#define PIPEnCTR	0x0070
63
64/* SYSCFG */
65#define SCKE	(1 << 10)	/* USB Module Clock Enable */
66#define HSE	(1 << 7)	/* High-Speed Operation Enable */
67#define DCFM	(1 << 6)	/* Controller Function Select */
68#define DRPD	(1 << 5)	/* D+ Line/D- Line Resistance Control */
69#define DPRPU	(1 << 4)	/* D+ Line Resistance Control */
70#define USBE	(1 << 0)	/* USB Module Operation Enable */
71
72/* DVSTCTR */
73#define EXTLP	(1 << 10)	/* Controls the EXTLP pin output state */
74#define PWEN	(1 << 9)	/* Controls the PWEN pin output state */
75#define RHST	(0x7)		/* Reset Handshake */
76#define  RHST_LOW_SPEED  1	/* Low-speed connection */
77#define  RHST_FULL_SPEED 2	/* Full-speed connection */
78#define  RHST_HIGH_SPEED 3	/* High-speed connection */
79
80/* CFIFOSEL */
81#define MBW_32	(0x2 << 10)	/* CFIFO Port Access Bit Width */
82
83/* CFIFOCTR */
84#define BVAL	(1 << 15)	/* Buffer Memory Enable Flag */
85#define BCLR	(1 << 14)	/* CPU buffer clear */
86#define FRDY	(1 << 13)	/* FIFO Port Ready */
87#define DTLN_MASK (0x0FFF)	/* Receive Data Length */
88
89/* INTENB0 */
90#define VBSE	(1 << 15)	/* Enable IRQ VBUS_0 and VBUSIN_0 */
91#define RSME	(1 << 14)	/* Enable IRQ Resume */
92#define SOFE	(1 << 13)	/* Enable IRQ Frame Number Update */
93#define DVSE	(1 << 12)	/* Enable IRQ Device State Transition */
94#define CTRE	(1 << 11)	/* Enable IRQ Control Stage Transition */
95#define BEMPE	(1 << 10)	/* Enable IRQ Buffer Empty */
96#define NRDYE	(1 << 9)	/* Enable IRQ Buffer Not Ready Response */
97#define BRDYE	(1 << 8)	/* Enable IRQ Buffer Ready */
98
99/* INTENB1 */
100#define BCHGE	(1 << 14)	/* USB Bus Change Interrupt Enable */
101#define DTCHE	(1 << 12)	/* Disconnection Detect Interrupt Enable */
102#define ATTCHE	(1 << 11)	/* Connection Detect Interrupt Enable */
103#define EOFERRE	(1 << 6)	/* EOF Error Detect Interrupt Enable */
104#define SIGNE	(1 << 5)	/* Setup Transaction Error Interrupt Enable */
105#define SACKE	(1 << 4)	/* Setup Transaction ACK Interrupt Enable */
106
107/* INTSTS0 */
108#define VBINT	(1 << 15)	/* VBUS0_0 and VBUS1_0 Interrupt Status */
109#define DVST	(1 << 12)	/* Device State Transition Interrupt Status */
110#define CTRT	(1 << 11)	/* Control Stage Interrupt Status */
111#define BEMP	(1 << 10)	/* Buffer Empty Interrupt Status */
112#define BRDY	(1 << 8)	/* Buffer Ready Interrupt Status */
113#define VBSTS	(1 << 7)	/* VBUS_0 and VBUSIN_0 Input Status */
114#define VALID	(1 << 3)	/* USB Request Receive */
115
116#define DVSQ_MASK		(0x3 << 4)	/* Device State */
117#define  POWER_STATE		(0 << 4)
118#define  DEFAULT_STATE		(1 << 4)
119#define  ADDRESS_STATE		(2 << 4)
120#define  CONFIGURATION_STATE	(3 << 4)
121
122#define CTSQ_MASK		(0x7)	/* Control Transfer Stage */
123#define  IDLE_SETUP_STAGE	0	/* Idle stage or setup stage */
124#define  READ_DATA_STAGE	1	/* Control read data stage */
125#define  READ_STATUS_STAGE	2	/* Control read status stage */
126#define  WRITE_DATA_STAGE	3	/* Control write data stage */
127#define  WRITE_STATUS_STAGE	4	/* Control write status stage */
128#define  NODATA_STATUS_STAGE	5	/* Control write NoData status stage */
129#define  SEQUENCE_ERROR		6	/* Control transfer sequence error */
130
131/* PIPECFG */
132/* DCPCFG */
133#define TYPE_NONE	(0 << 14)	/* Transfer Type */
134#define TYPE_BULK	(1 << 14)
135#define TYPE_INT	(2 << 14)
136#define TYPE_ISO	(3 << 14)
137#define DBLB		(1 << 9)	/* Double Buffer Mode */
138#define SHTNAK		(1 << 7)	/* Pipe Disable in Transfer End */
139#define DIR_OUT		(1 << 4)	/* Transfer Direction */
140
141/* PIPEMAXP */
142/* DCPMAXP */
143#define DEVSEL_MASK	(0xF << 12)	/* Device Select */
144#define DCP_MAXP_MASK	(0x7F)
145#define PIPE_MAXP_MASK	(0x7FF)
146
147/* PIPEBUF */
148#define BUFSIZE_SHIFT	10
149#define BUFSIZE_MASK	(0x1F << BUFSIZE_SHIFT)
150#define BUFNMB_MASK	(0xFF)
151
152/* PIPEnCTR */
153/* DCPCTR */
154#define BSTS		(1 << 15)	/* Buffer Status */
155#define CSSTS		(1 << 12)	/* CSSTS Status */
156#define SQCLR		(1 << 8)	/* Toggle Bit Clear */
157#define	ACLRM		(1 << 9)	/* Buffer Auto-Clear Mode */
158#define PBUSY		(1 << 5)	/* Pipe Busy */
159#define PID_MASK	(0x3)		/* Response PID */
160#define  PID_NAK	0
161#define  PID_BUF	1
162#define  PID_STALL10	2
163#define  PID_STALL11	3
164
165#define CCPL		(1 << 2)	/* Control Transfer End Enable */
166
167/* FRMNUM */
168#define FRNM_MASK	(0x7FF)
169
170/*
171 *		struct
172 */
173struct usbhs_priv {
174
175	void __iomem *base;
176	unsigned int irq;
177
178	struct renesas_usbhs_platform_callback	*pfunc;
179	struct renesas_usbhs_driver_param	*dparam;
180
181	struct delayed_work notify_hotplug_work;
182	struct platform_device *pdev;
183
184	spinlock_t		lock;
185
186	u32 flags;
187
188	/*
189	 * module control
190	 */
191	struct usbhs_mod_info mod_info;
192
193	/*
194	 * pipe control
195	 */
196	struct usbhs_pipe_info pipe_info;
197};
198
199/*
200 * common
201 */
202u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
203void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
204void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
205
206int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev);
207/*
208 * sysconfig
209 */
210void usbhs_sys_clock_ctrl(struct usbhs_priv *priv, int enable);
211void usbhs_sys_hispeed_ctrl(struct usbhs_priv *priv, int enable);
212void usbhs_sys_usb_ctrl(struct usbhs_priv *priv, int enable);
213void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
214void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
215
216/*
217 * frame
218 */
219int usbhs_frame_get_num(struct usbhs_priv *priv);
220
221/*
222 * data
223 */
224struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
225#define usbhs_get_dparam(priv, param)	(priv->dparam->param)
226#define usbhs_priv_to_pdev(priv)	(priv->pdev)
227#define usbhs_priv_to_dev(priv)		(&priv->pdev->dev)
228#define usbhs_priv_to_lock(priv)	(&priv->lock)
229
230#endif /* RENESAS_USB_DRIVER_H */
231