common.h revision e8d548d549688d335236f7f6f8bcee141a207ff8 
1/*
2 * Renesas USB driver
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
15 *
16 */
17#ifndef RENESAS_USB_DRIVER_H
18#define RENESAS_USB_DRIVER_H
19
20#include <linux/platform_device.h>
21#include <linux/usb/renesas_usbhs.h>
22
23struct usbhs_priv;
24
25#include "./mod.h"
26#include "./pipe.h"
27#include "./fifo.h"
28
29/*
30 *
31 *		register define
32 *
33 */
34#define SYSCFG		0x0000
35#define BUSWAIT		0x0002
36#define DVSTCTR		0x0008
37#define CFIFO		0x0014
38#define CFIFOSEL	0x0020
39#define CFIFOCTR	0x0022
40#define INTENB0		0x0030
41#define INTENB1		0x0032
42#define BRDYENB		0x0036
43#define NRDYENB		0x0038
44#define BEMPENB		0x003A
45#define INTSTS0		0x0040
46#define INTSTS1		0x0042
47#define BRDYSTS		0x0046
48#define NRDYSTS		0x0048
49#define BEMPSTS		0x004A
50#define FRMNUM		0x004C
51#define USBREQ		0x0054	/* USB request type register */
52#define USBVAL		0x0056	/* USB request value register */
53#define USBINDX		0x0058	/* USB request index register */
54#define USBLENG		0x005A	/* USB request length register */
55#define DCPCFG		0x005C
56#define DCPMAXP		0x005E
57#define DCPCTR		0x0060
58#define PIPESEL		0x0064
59#define PIPECFG		0x0068
60#define PIPEBUF		0x006A
61#define PIPEMAXP	0x006C
62#define PIPEPERI	0x006E
63#define PIPEnCTR	0x0070
64
65/* SYSCFG */
66#define SCKE	(1 << 10)	/* USB Module Clock Enable */
67#define HSE	(1 << 7)	/* High-Speed Operation Enable */
68#define DCFM	(1 << 6)	/* Controller Function Select */
69#define DRPD	(1 << 5)	/* D+ Line/D- Line Resistance Control */
70#define DPRPU	(1 << 4)	/* D+ Line Resistance Control */
71#define USBE	(1 << 0)	/* USB Module Operation Enable */
72
73/* DVSTCTR */
74#define EXTLP	(1 << 10)	/* Controls the EXTLP pin output state */
75#define PWEN	(1 << 9)	/* Controls the PWEN pin output state */
76#define RHST	(0x7)		/* Reset Handshake */
77#define  RHST_LOW_SPEED  1	/* Low-speed connection */
78#define  RHST_FULL_SPEED 2	/* Full-speed connection */
79#define  RHST_HIGH_SPEED 3	/* High-speed connection */
80
81/* CFIFOSEL */
82#define MBW_32	(0x2 << 10)	/* CFIFO Port Access Bit Width */
83
84/* CFIFOCTR */
85#define BVAL	(1 << 15)	/* Buffer Memory Enable Flag */
86#define BCLR	(1 << 14)	/* CPU buffer clear */
87#define FRDY	(1 << 13)	/* FIFO Port Ready */
88#define DTLN_MASK (0x0FFF)	/* Receive Data Length */
89
90/* INTENB0 */
91#define VBSE	(1 << 15)	/* Enable IRQ VBUS_0 and VBUSIN_0 */
92#define RSME	(1 << 14)	/* Enable IRQ Resume */
93#define SOFE	(1 << 13)	/* Enable IRQ Frame Number Update */
94#define DVSE	(1 << 12)	/* Enable IRQ Device State Transition */
95#define CTRE	(1 << 11)	/* Enable IRQ Control Stage Transition */
96#define BEMPE	(1 << 10)	/* Enable IRQ Buffer Empty */
97#define NRDYE	(1 << 9)	/* Enable IRQ Buffer Not Ready Response */
98#define BRDYE	(1 << 8)	/* Enable IRQ Buffer Ready */
99
100/* INTENB1 */
101#define BCHGE	(1 << 14)	/* USB Bus Change Interrupt Enable */
102#define DTCHE	(1 << 12)	/* Disconnection Detect Interrupt Enable */
103#define ATTCHE	(1 << 11)	/* Connection Detect Interrupt Enable */
104#define EOFERRE	(1 << 6)	/* EOF Error Detect Interrupt Enable */
105#define SIGNE	(1 << 5)	/* Setup Transaction Error Interrupt Enable */
106#define SACKE	(1 << 4)	/* Setup Transaction ACK Interrupt Enable */
107
108/* INTSTS0 */
109#define VBINT	(1 << 15)	/* VBUS0_0 and VBUS1_0 Interrupt Status */
110#define DVST	(1 << 12)	/* Device State Transition Interrupt Status */
111#define CTRT	(1 << 11)	/* Control Stage Interrupt Status */
112#define BEMP	(1 << 10)	/* Buffer Empty Interrupt Status */
113#define BRDY	(1 << 8)	/* Buffer Ready Interrupt Status */
114#define VBSTS	(1 << 7)	/* VBUS_0 and VBUSIN_0 Input Status */
115#define VALID	(1 << 3)	/* USB Request Receive */
116
117#define DVSQ_MASK		(0x3 << 4)	/* Device State */
118#define  POWER_STATE		(0 << 4)
119#define  DEFAULT_STATE		(1 << 4)
120#define  ADDRESS_STATE		(2 << 4)
121#define  CONFIGURATION_STATE	(3 << 4)
122
123#define CTSQ_MASK		(0x7)	/* Control Transfer Stage */
124#define  IDLE_SETUP_STAGE	0	/* Idle stage or setup stage */
125#define  READ_DATA_STAGE	1	/* Control read data stage */
126#define  READ_STATUS_STAGE	2	/* Control read status stage */
127#define  WRITE_DATA_STAGE	3	/* Control write data stage */
128#define  WRITE_STATUS_STAGE	4	/* Control write status stage */
129#define  NODATA_STATUS_STAGE	5	/* Control write NoData status stage */
130#define  SEQUENCE_ERROR		6	/* Control transfer sequence error */
131
132/* PIPECFG */
133/* DCPCFG */
134#define TYPE_NONE	(0 << 14)	/* Transfer Type */
135#define TYPE_BULK	(1 << 14)
136#define TYPE_INT	(2 << 14)
137#define TYPE_ISO	(3 << 14)
138#define DBLB		(1 << 9)	/* Double Buffer Mode */
139#define SHTNAK		(1 << 7)	/* Pipe Disable in Transfer End */
140#define DIR_OUT		(1 << 4)	/* Transfer Direction */
141
142/* PIPEMAXP */
143/* DCPMAXP */
144#define DEVSEL_MASK	(0xF << 12)	/* Device Select */
145#define DCP_MAXP_MASK	(0x7F)
146#define PIPE_MAXP_MASK	(0x7FF)
147
148/* PIPEBUF */
149#define BUFSIZE_SHIFT	10
150#define BUFSIZE_MASK	(0x1F << BUFSIZE_SHIFT)
151#define BUFNMB_MASK	(0xFF)
152
153/* PIPEnCTR */
154/* DCPCTR */
155#define BSTS		(1 << 15)	/* Buffer Status */
156#define CSSTS		(1 << 12)	/* CSSTS Status */
157#define SQCLR		(1 << 8)	/* Toggle Bit Clear */
158#define	ACLRM		(1 << 9)	/* Buffer Auto-Clear Mode */
159#define PBUSY		(1 << 5)	/* Pipe Busy */
160#define PID_MASK	(0x3)		/* Response PID */
161#define  PID_NAK	0
162#define  PID_BUF	1
163#define  PID_STALL10	2
164#define  PID_STALL11	3
165
166#define CCPL		(1 << 2)	/* Control Transfer End Enable */
167
168/* FRMNUM */
169#define FRNM_MASK	(0x7FF)
170
171/*
172 *		struct
173 */
174struct usbhs_priv {
175
176	void __iomem *base;
177	unsigned int irq;
178
179	struct renesas_usbhs_platform_callback	*pfunc;
180	struct renesas_usbhs_driver_param	*dparam;
181
182	struct delayed_work notify_hotplug_work;
183	struct platform_device *pdev;
184
185	spinlock_t		lock;
186
187	u32 flags;
188
189	/*
190	 * module control
191	 */
192	struct usbhs_mod_info mod_info;
193
194	/*
195	 * pipe control
196	 */
197	struct usbhs_pipe_info pipe_info;
198};
199
200/*
201 * common
202 */
203u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
204void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
205void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
206
207int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev);
208/*
209 * sysconfig
210 */
211void usbhs_sys_clock_ctrl(struct usbhs_priv *priv, int enable);
212void usbhs_sys_hispeed_ctrl(struct usbhs_priv *priv, int enable);
213void usbhs_sys_usb_ctrl(struct usbhs_priv *priv, int enable);
214void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
215void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
216
217/*
218 * frame
219 */
220int usbhs_frame_get_num(struct usbhs_priv *priv);
221
222/*
223 * data
224 */
225struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
226#define usbhs_get_dparam(priv, param)	(priv->dparam->param)
227#define usbhs_priv_to_pdev(priv)	(priv->pdev)
228#define usbhs_priv_to_dev(priv)		(&priv->pdev->dev)
229#define usbhs_priv_to_lock(priv)	(&priv->lock)
230
231#endif /* RENESAS_USB_DRIVER_H */
232