common.h revision eb05191f6a9aba8344a0d5f28642b5ecf44d49a4 
1/*
2 * Renesas USB driver
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
15 *
16 */
17#ifndef RENESAS_USB_DRIVER_H
18#define RENESAS_USB_DRIVER_H
19
20#include <linux/platform_device.h>
21#include <linux/usb/renesas_usbhs.h>
22
23struct usbhs_priv;
24
25#include "./mod.h"
26#include "./pipe.h"
27
28/*
29 *
30 *		register define
31 *
32 */
33#define SYSCFG		0x0000
34#define BUSWAIT		0x0002
35#define DVSTCTR		0x0008
36#define CFIFO		0x0014
37#define CFIFOSEL	0x0020
38#define CFIFOCTR	0x0022
39#define D0FIFO		0x0100
40#define D0FIFOSEL	0x0028
41#define D0FIFOCTR	0x002A
42#define D1FIFO		0x0120
43#define D1FIFOSEL	0x002C
44#define D1FIFOCTR	0x002E
45#define INTENB0		0x0030
46#define INTENB1		0x0032
47#define BRDYENB		0x0036
48#define NRDYENB		0x0038
49#define BEMPENB		0x003A
50#define INTSTS0		0x0040
51#define INTSTS1		0x0042
52#define BRDYSTS		0x0046
53#define NRDYSTS		0x0048
54#define BEMPSTS		0x004A
55#define FRMNUM		0x004C
56#define USBREQ		0x0054	/* USB request type register */
57#define USBVAL		0x0056	/* USB request value register */
58#define USBINDX		0x0058	/* USB request index register */
59#define USBLENG		0x005A	/* USB request length register */
60#define DCPCFG		0x005C
61#define DCPMAXP		0x005E
62#define DCPCTR		0x0060
63#define PIPESEL		0x0064
64#define PIPECFG		0x0068
65#define PIPEBUF		0x006A
66#define PIPEMAXP	0x006C
67#define PIPEPERI	0x006E
68#define PIPEnCTR	0x0070
69#define PIPE1TRE	0x0090
70#define PIPE1TRN	0x0092
71#define PIPE2TRE	0x0094
72#define PIPE2TRN	0x0096
73#define PIPE3TRE	0x0098
74#define PIPE3TRN	0x009A
75#define PIPE4TRE	0x009C
76#define PIPE4TRN	0x009E
77#define PIPE5TRE	0x00A0
78#define PIPE5TRN	0x00A2
79#define PIPEBTRE	0x00A4
80#define PIPEBTRN	0x00A6
81#define PIPECTRE	0x00A8
82#define PIPECTRN	0x00AA
83#define PIPEDTRE	0x00AC
84#define PIPEDTRN	0x00AE
85#define PIPEETRE	0x00B0
86#define PIPEETRN	0x00B2
87#define PIPEFTRE	0x00B4
88#define PIPEFTRN	0x00B6
89#define PIPE9TRE	0x00B8
90#define PIPE9TRN	0x00BA
91#define PIPEATRE	0x00BC
92#define PIPEATRN	0x00BE
93#define DEVADD0		0x00D0 /* Device address n configuration */
94#define DEVADD1		0x00D2
95#define DEVADD2		0x00D4
96#define DEVADD3		0x00D6
97#define DEVADD4		0x00D8
98#define DEVADD5		0x00DA
99#define DEVADD6		0x00DC
100#define DEVADD7		0x00DE
101#define DEVADD8		0x00E0
102#define DEVADD9		0x00E2
103#define DEVADDA		0x00E4
104
105/* SYSCFG */
106#define SCKE	(1 << 10)	/* USB Module Clock Enable */
107#define HSE	(1 << 7)	/* High-Speed Operation Enable */
108#define DCFM	(1 << 6)	/* Controller Function Select */
109#define DRPD	(1 << 5)	/* D+ Line/D- Line Resistance Control */
110#define DPRPU	(1 << 4)	/* D+ Line Resistance Control */
111#define USBE	(1 << 0)	/* USB Module Operation Enable */
112
113/* DVSTCTR */
114#define EXTLP	(1 << 10)	/* Controls the EXTLP pin output state */
115#define PWEN	(1 << 9)	/* Controls the PWEN pin output state */
116#define USBRST	(1 << 6)	/* Bus Reset Output */
117#define UACT	(1 << 4)	/* USB Bus Enable */
118#define RHST	(0x7)		/* Reset Handshake */
119#define  RHST_LOW_SPEED  1	/* Low-speed connection */
120#define  RHST_FULL_SPEED 2	/* Full-speed connection */
121#define  RHST_HIGH_SPEED 3	/* High-speed connection */
122
123/* CFIFOSEL */
124#define DREQE	(1 << 12)	/* DMA Transfer Request Enable */
125#define MBW_32	(0x2 << 10)	/* CFIFO Port Access Bit Width */
126
127/* CFIFOCTR */
128#define BVAL	(1 << 15)	/* Buffer Memory Enable Flag */
129#define BCLR	(1 << 14)	/* CPU buffer clear */
130#define FRDY	(1 << 13)	/* FIFO Port Ready */
131#define DTLN_MASK (0x0FFF)	/* Receive Data Length */
132
133/* INTENB0 */
134#define VBSE	(1 << 15)	/* Enable IRQ VBUS_0 and VBUSIN_0 */
135#define RSME	(1 << 14)	/* Enable IRQ Resume */
136#define SOFE	(1 << 13)	/* Enable IRQ Frame Number Update */
137#define DVSE	(1 << 12)	/* Enable IRQ Device State Transition */
138#define CTRE	(1 << 11)	/* Enable IRQ Control Stage Transition */
139#define BEMPE	(1 << 10)	/* Enable IRQ Buffer Empty */
140#define NRDYE	(1 << 9)	/* Enable IRQ Buffer Not Ready Response */
141#define BRDYE	(1 << 8)	/* Enable IRQ Buffer Ready */
142
143/* INTENB1 */
144#define BCHGE	(1 << 14)	/* USB Bus Change Interrupt Enable */
145#define DTCHE	(1 << 12)	/* Disconnection Detect Interrupt Enable */
146#define ATTCHE	(1 << 11)	/* Connection Detect Interrupt Enable */
147#define EOFERRE	(1 << 6)	/* EOF Error Detect Interrupt Enable */
148#define SIGNE	(1 << 5)	/* Setup Transaction Error Interrupt Enable */
149#define SACKE	(1 << 4)	/* Setup Transaction ACK Interrupt Enable */
150
151/* INTSTS0 */
152#define VBINT	(1 << 15)	/* VBUS0_0 and VBUS1_0 Interrupt Status */
153#define DVST	(1 << 12)	/* Device State Transition Interrupt Status */
154#define CTRT	(1 << 11)	/* Control Stage Interrupt Status */
155#define BEMP	(1 << 10)	/* Buffer Empty Interrupt Status */
156#define BRDY	(1 << 8)	/* Buffer Ready Interrupt Status */
157#define VBSTS	(1 << 7)	/* VBUS_0 and VBUSIN_0 Input Status */
158#define VALID	(1 << 3)	/* USB Request Receive */
159
160#define DVSQ_MASK		(0x3 << 4)	/* Device State */
161#define  POWER_STATE		(0 << 4)
162#define  DEFAULT_STATE		(1 << 4)
163#define  ADDRESS_STATE		(2 << 4)
164#define  CONFIGURATION_STATE	(3 << 4)
165
166#define CTSQ_MASK		(0x7)	/* Control Transfer Stage */
167#define  IDLE_SETUP_STAGE	0	/* Idle stage or setup stage */
168#define  READ_DATA_STAGE	1	/* Control read data stage */
169#define  READ_STATUS_STAGE	2	/* Control read status stage */
170#define  WRITE_DATA_STAGE	3	/* Control write data stage */
171#define  WRITE_STATUS_STAGE	4	/* Control write status stage */
172#define  NODATA_STATUS_STAGE	5	/* Control write NoData status stage */
173#define  SEQUENCE_ERROR		6	/* Control transfer sequence error */
174
175/* PIPECFG */
176/* DCPCFG */
177#define TYPE_NONE	(0 << 14)	/* Transfer Type */
178#define TYPE_BULK	(1 << 14)
179#define TYPE_INT	(2 << 14)
180#define TYPE_ISO	(3 << 14)
181#define DBLB		(1 << 9)	/* Double Buffer Mode */
182#define SHTNAK		(1 << 7)	/* Pipe Disable in Transfer End */
183#define DIR_OUT		(1 << 4)	/* Transfer Direction */
184
185/* PIPEMAXP */
186/* DCPMAXP */
187#define DEVSEL_MASK	(0xF << 12)	/* Device Select */
188#define DCP_MAXP_MASK	(0x7F)
189#define PIPE_MAXP_MASK	(0x7FF)
190
191/* PIPEBUF */
192#define BUFSIZE_SHIFT	10
193#define BUFSIZE_MASK	(0x1F << BUFSIZE_SHIFT)
194#define BUFNMB_MASK	(0xFF)
195
196/* PIPEnCTR */
197/* DCPCTR */
198#define BSTS		(1 << 15)	/* Buffer Status */
199#define SUREQ		(1 << 14)	/* Sending SETUP Token */
200#define CSSTS		(1 << 12)	/* CSSTS Status */
201#define	ACLRM		(1 << 9)	/* Buffer Auto-Clear Mode */
202#define SQCLR		(1 << 8)	/* Toggle Bit Clear */
203#define SQSET		(1 << 7)	/* Toggle Bit Set */
204#define PBUSY		(1 << 5)	/* Pipe Busy */
205#define PID_MASK	(0x3)		/* Response PID */
206#define  PID_NAK	0
207#define  PID_BUF	1
208#define  PID_STALL10	2
209#define  PID_STALL11	3
210
211#define CCPL		(1 << 2)	/* Control Transfer End Enable */
212
213/* PIPEnTRE */
214#define TRENB		(1 << 9)	/* Transaction Counter Enable */
215#define TRCLR		(1 << 8)	/* Transaction Counter Clear */
216
217/* FRMNUM */
218#define FRNM_MASK	(0x7FF)
219
220/* DEVADDn */
221#define UPPHUB(x)	(((x) & 0xF) << 11)	/* HUB Register */
222#define HUBPORT(x)	(((x) & 0x7) << 8)	/* HUB Port for Target Device */
223#define USBSPD(x)	(((x) & 0x3) << 6)	/* Device Transfer Rate */
224#define USBSPD_SPEED_LOW	0x1
225#define USBSPD_SPEED_FULL	0x2
226#define USBSPD_SPEED_HIGH	0x3
227
228/*
229 *		struct
230 */
231struct usbhs_priv {
232
233	void __iomem *base;
234	unsigned int irq;
235
236	struct renesas_usbhs_platform_callback	*pfunc;
237	struct renesas_usbhs_driver_param	*dparam;
238
239	struct delayed_work notify_hotplug_work;
240	struct platform_device *pdev;
241
242	spinlock_t		lock;
243
244	u32 flags;
245
246	/*
247	 * module control
248	 */
249	struct usbhs_mod_info mod_info;
250
251	/*
252	 * pipe control
253	 */
254	struct usbhs_pipe_info pipe_info;
255
256	/*
257	 * fifo control
258	 */
259	struct usbhs_fifo_info fifo_info;
260};
261
262/*
263 * common
264 */
265u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
266void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
267void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
268
269int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev);
270
271#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f)
272#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f)
273
274/*
275 * sysconfig
276 */
277void usbhs_sys_clock_ctrl(struct usbhs_priv *priv, int enable);
278void usbhs_sys_hispeed_ctrl(struct usbhs_priv *priv, int enable);
279void usbhs_sys_usb_ctrl(struct usbhs_priv *priv, int enable);
280void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
281void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
282
283/*
284 * usb request
285 */
286void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
287void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
288
289/*
290 * bus
291 */
292void usbhs_bus_send_sof_enable(struct usbhs_priv *priv);
293void usbhs_bus_send_reset(struct usbhs_priv *priv);
294int usbhs_bus_get_speed(struct usbhs_priv *priv);
295int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
296
297/*
298 * frame
299 */
300int usbhs_frame_get_num(struct usbhs_priv *priv);
301
302/*
303 * device config
304 */
305int usbhs_set_device_speed(struct usbhs_priv *priv, int devnum, u16 upphub,
306			   u16 hubport, u16 speed);
307
308/*
309 * data
310 */
311struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
312#define usbhs_get_dparam(priv, param)	(priv->dparam->param)
313#define usbhs_priv_to_pdev(priv)	(priv->pdev)
314#define usbhs_priv_to_dev(priv)		(&priv->pdev->dev)
315#define usbhs_priv_to_lock(priv)	(&priv->lock)
316
317#endif /* RENESAS_USB_DRIVER_H */
318