common.h revision ef8bedb9048c293dfa85ac36482a1970646a8272
1/* 2 * Renesas USB driver 3 * 4 * Copyright (C) 2011 Renesas Solutions Corp. 5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 15 * 16 */ 17#ifndef RENESAS_USB_DRIVER_H 18#define RENESAS_USB_DRIVER_H 19 20#include <linux/platform_device.h> 21#include <linux/usb/renesas_usbhs.h> 22 23struct usbhs_priv; 24 25#include "./mod.h" 26#include "./pipe.h" 27 28/* 29 * 30 * register define 31 * 32 */ 33#define SYSCFG 0x0000 34#define BUSWAIT 0x0002 35#define DVSTCTR 0x0008 36#define CFIFO 0x0014 37#define CFIFOSEL 0x0020 38#define CFIFOCTR 0x0022 39#define D0FIFO 0x0100 40#define D0FIFOSEL 0x0028 41#define D0FIFOCTR 0x002A 42#define D1FIFO 0x0120 43#define D1FIFOSEL 0x002C 44#define D1FIFOCTR 0x002E 45#define INTENB0 0x0030 46#define INTENB1 0x0032 47#define BRDYENB 0x0036 48#define NRDYENB 0x0038 49#define BEMPENB 0x003A 50#define INTSTS0 0x0040 51#define INTSTS1 0x0042 52#define BRDYSTS 0x0046 53#define NRDYSTS 0x0048 54#define BEMPSTS 0x004A 55#define FRMNUM 0x004C 56#define USBREQ 0x0054 /* USB request type register */ 57#define USBVAL 0x0056 /* USB request value register */ 58#define USBINDX 0x0058 /* USB request index register */ 59#define USBLENG 0x005A /* USB request length register */ 60#define DCPCFG 0x005C 61#define DCPMAXP 0x005E 62#define DCPCTR 0x0060 63#define PIPESEL 0x0064 64#define PIPECFG 0x0068 65#define PIPEBUF 0x006A 66#define PIPEMAXP 0x006C 67#define PIPEPERI 0x006E 68#define PIPEnCTR 0x0070 69#define PIPE1TRE 0x0090 70#define PIPE1TRN 0x0092 71#define PIPE2TRE 0x0094 72#define PIPE2TRN 0x0096 73#define PIPE3TRE 0x0098 74#define PIPE3TRN 0x009A 75#define PIPE4TRE 0x009C 76#define PIPE4TRN 0x009E 77#define PIPE5TRE 0x00A0 78#define PIPE5TRN 0x00A2 79#define PIPEBTRE 0x00A4 80#define PIPEBTRN 0x00A6 81#define PIPECTRE 0x00A8 82#define PIPECTRN 0x00AA 83#define PIPEDTRE 0x00AC 84#define PIPEDTRN 0x00AE 85#define PIPEETRE 0x00B0 86#define PIPEETRN 0x00B2 87#define PIPEFTRE 0x00B4 88#define PIPEFTRN 0x00B6 89#define PIPE9TRE 0x00B8 90#define PIPE9TRN 0x00BA 91#define PIPEATRE 0x00BC 92#define PIPEATRN 0x00BE 93 94/* SYSCFG */ 95#define SCKE (1 << 10) /* USB Module Clock Enable */ 96#define HSE (1 << 7) /* High-Speed Operation Enable */ 97#define DCFM (1 << 6) /* Controller Function Select */ 98#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */ 99#define DPRPU (1 << 4) /* D+ Line Resistance Control */ 100#define USBE (1 << 0) /* USB Module Operation Enable */ 101 102/* DVSTCTR */ 103#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */ 104#define PWEN (1 << 9) /* Controls the PWEN pin output state */ 105#define USBRST (1 << 6) /* Bus Reset Output */ 106#define UACT (1 << 4) /* USB Bus Enable */ 107#define RHST (0x7) /* Reset Handshake */ 108#define RHST_LOW_SPEED 1 /* Low-speed connection */ 109#define RHST_FULL_SPEED 2 /* Full-speed connection */ 110#define RHST_HIGH_SPEED 3 /* High-speed connection */ 111 112/* CFIFOSEL */ 113#define DREQE (1 << 12) /* DMA Transfer Request Enable */ 114#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */ 115 116/* CFIFOCTR */ 117#define BVAL (1 << 15) /* Buffer Memory Enable Flag */ 118#define BCLR (1 << 14) /* CPU buffer clear */ 119#define FRDY (1 << 13) /* FIFO Port Ready */ 120#define DTLN_MASK (0x0FFF) /* Receive Data Length */ 121 122/* INTENB0 */ 123#define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */ 124#define RSME (1 << 14) /* Enable IRQ Resume */ 125#define SOFE (1 << 13) /* Enable IRQ Frame Number Update */ 126#define DVSE (1 << 12) /* Enable IRQ Device State Transition */ 127#define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */ 128#define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */ 129#define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */ 130#define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */ 131 132/* INTENB1 */ 133#define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */ 134#define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */ 135#define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */ 136#define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */ 137#define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */ 138#define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */ 139 140/* INTSTS0 */ 141#define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */ 142#define DVST (1 << 12) /* Device State Transition Interrupt Status */ 143#define CTRT (1 << 11) /* Control Stage Interrupt Status */ 144#define BEMP (1 << 10) /* Buffer Empty Interrupt Status */ 145#define BRDY (1 << 8) /* Buffer Ready Interrupt Status */ 146#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */ 147#define VALID (1 << 3) /* USB Request Receive */ 148 149#define DVSQ_MASK (0x3 << 4) /* Device State */ 150#define POWER_STATE (0 << 4) 151#define DEFAULT_STATE (1 << 4) 152#define ADDRESS_STATE (2 << 4) 153#define CONFIGURATION_STATE (3 << 4) 154 155#define CTSQ_MASK (0x7) /* Control Transfer Stage */ 156#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */ 157#define READ_DATA_STAGE 1 /* Control read data stage */ 158#define READ_STATUS_STAGE 2 /* Control read status stage */ 159#define WRITE_DATA_STAGE 3 /* Control write data stage */ 160#define WRITE_STATUS_STAGE 4 /* Control write status stage */ 161#define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */ 162#define SEQUENCE_ERROR 6 /* Control transfer sequence error */ 163 164/* PIPECFG */ 165/* DCPCFG */ 166#define TYPE_NONE (0 << 14) /* Transfer Type */ 167#define TYPE_BULK (1 << 14) 168#define TYPE_INT (2 << 14) 169#define TYPE_ISO (3 << 14) 170#define DBLB (1 << 9) /* Double Buffer Mode */ 171#define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */ 172#define DIR_OUT (1 << 4) /* Transfer Direction */ 173 174/* PIPEMAXP */ 175/* DCPMAXP */ 176#define DEVSEL_MASK (0xF << 12) /* Device Select */ 177#define DCP_MAXP_MASK (0x7F) 178#define PIPE_MAXP_MASK (0x7FF) 179 180/* PIPEBUF */ 181#define BUFSIZE_SHIFT 10 182#define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT) 183#define BUFNMB_MASK (0xFF) 184 185/* PIPEnCTR */ 186/* DCPCTR */ 187#define BSTS (1 << 15) /* Buffer Status */ 188#define SUREQ (1 << 14) /* Sending SETUP Token */ 189#define CSSTS (1 << 12) /* CSSTS Status */ 190#define SQCLR (1 << 8) /* Toggle Bit Clear */ 191#define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */ 192#define PBUSY (1 << 5) /* Pipe Busy */ 193#define PID_MASK (0x3) /* Response PID */ 194#define PID_NAK 0 195#define PID_BUF 1 196#define PID_STALL10 2 197#define PID_STALL11 3 198 199#define CCPL (1 << 2) /* Control Transfer End Enable */ 200 201/* PIPEnTRE */ 202#define TRENB (1 << 9) /* Transaction Counter Enable */ 203#define TRCLR (1 << 8) /* Transaction Counter Clear */ 204 205/* FRMNUM */ 206#define FRNM_MASK (0x7FF) 207 208/* 209 * struct 210 */ 211struct usbhs_priv { 212 213 void __iomem *base; 214 unsigned int irq; 215 216 struct renesas_usbhs_platform_callback *pfunc; 217 struct renesas_usbhs_driver_param *dparam; 218 219 struct delayed_work notify_hotplug_work; 220 struct platform_device *pdev; 221 222 spinlock_t lock; 223 224 u32 flags; 225 226 /* 227 * module control 228 */ 229 struct usbhs_mod_info mod_info; 230 231 /* 232 * pipe control 233 */ 234 struct usbhs_pipe_info pipe_info; 235 236 /* 237 * fifo control 238 */ 239 struct usbhs_fifo_info fifo_info; 240}; 241 242/* 243 * common 244 */ 245u16 usbhs_read(struct usbhs_priv *priv, u32 reg); 246void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data); 247void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data); 248 249int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev); 250 251#define usbhs_lock(p, f) spin_lock_irqsave(usbhs_priv_to_lock(p), f) 252#define usbhs_unlock(p, f) spin_unlock_irqrestore(usbhs_priv_to_lock(p), f) 253 254/* 255 * sysconfig 256 */ 257void usbhs_sys_clock_ctrl(struct usbhs_priv *priv, int enable); 258void usbhs_sys_hispeed_ctrl(struct usbhs_priv *priv, int enable); 259void usbhs_sys_usb_ctrl(struct usbhs_priv *priv, int enable); 260void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable); 261void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable); 262 263/* 264 * usb request 265 */ 266void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req); 267void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req); 268 269/* 270 * bus 271 */ 272void usbhs_bus_send_sof_enable(struct usbhs_priv *priv); 273void usbhs_bus_send_reset(struct usbhs_priv *priv); 274int usbhs_bus_get_speed(struct usbhs_priv *priv); 275int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable); 276 277/* 278 * frame 279 */ 280int usbhs_frame_get_num(struct usbhs_priv *priv); 281 282/* 283 * data 284 */ 285struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev); 286#define usbhs_get_dparam(priv, param) (priv->dparam->param) 287#define usbhs_priv_to_pdev(priv) (priv->pdev) 288#define usbhs_priv_to_dev(priv) (&priv->pdev->dev) 289#define usbhs_priv_to_lock(priv) (&priv->lock) 290 291#endif /* RENESAS_USB_DRIVER_H */ 292