11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * BRIEF MODULE DESCRIPTION 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Hardware definitions for the Au1100 LCD controller 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2002 MontaVista Software 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 2002 Alchemy Semiconductor 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Author: Alchemy Semiconductor, MontaVista Software 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify it 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * under the terms of the GNU General Public License as published by the 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Free Software Foundation; either version 2 of the License, or (at your 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * option) any later version. 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * You should have received a copy of the GNU General Public License along 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * with this program; if not, write to the Free Software Foundation, Inc., 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 675 Mass Ave, Cambridge, MA 02139, USA. 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef _AU1100LCD_H 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define _AU1100LCD_H 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 333b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#include <asm/mach-au1x00/au1000.h> 343b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 353b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg) 363b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg) 373b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg) 383b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 393b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#if DEBUG 403b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg) 413b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#else 423b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define print_dbg(f, arg...) do {} while (0) 433b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#endif 443b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 453b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#if defined(__BIG_ENDIAN) 463b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11 473b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#else 483b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00 493b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#endif 503b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565 513b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/********************************************************************/ 533b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 543b495f2bb749b828499135743b9ddec46e34fda8Pete Popov/* LCD controller restrictions */ 553b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define AU1100_LCD_MAX_XRES 800 563b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define AU1100_LCD_MAX_YRES 600 573b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define AU1100_LCD_MAX_BPP 16 583b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define AU1100_LCD_MAX_CLK 48000000 593b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define AU1100_LCD_NBR_PALETTE_ENTRIES 256 603b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 613b495f2bb749b828499135743b9ddec46e34fda8Pete Popov/* Default number of visible screen buffer to allocate */ 623b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define AU1100FB_NBR_VIDEO_BUFFERS 4 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/********************************************************************/ 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 663b495f2bb749b828499135743b9ddec46e34fda8Pete Popovstruct au1100fb_panel 673b495f2bb749b828499135743b9ddec46e34fda8Pete Popov{ 683b495f2bb749b828499135743b9ddec46e34fda8Pete Popov const char name[25]; /* Full name <vendor>_<model> */ 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 703b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 control_base; /* Mode-independent control values */ 713b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 clkcontrol_base; /* Panel pixclock preferences */ 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 733b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 horztiming; 743b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 verttiming; 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 763b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 xres; /* Maximum horizontal resolution */ 773b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 yres; /* Maximum vertical resolution */ 783b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 bpp; /* Maximum depth supported */ 793b495f2bb749b828499135743b9ddec46e34fda8Pete Popov}; 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 813b495f2bb749b828499135743b9ddec46e34fda8Pete Popovstruct au1100fb_regs 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 833b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_control; 843b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_intstatus; 853b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_intenable; 863b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_horztiming; 873b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_verttiming; 883b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_clkcontrol; 893b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_dmaaddr0; 903b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_dmaaddr1; 913b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_words; 923b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_pwmdiv; 933b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_pwmhi; 943b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 reserved[(0x0400-0x002C)/4]; 953b495f2bb749b828499135743b9ddec46e34fda8Pete Popov u32 lcd_pallettebase[256]; 963b495f2bb749b828499135743b9ddec46e34fda8Pete Popov}; 973b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 983b495f2bb749b828499135743b9ddec46e34fda8Pete Popovstruct au1100fb_device { 993b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 1003b495f2bb749b828499135743b9ddec46e34fda8Pete Popov struct fb_info info; /* FB driver info record */ 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1023b495f2bb749b828499135743b9ddec46e34fda8Pete Popov struct au1100fb_panel *panel; /* Panel connected to this device */ 1033b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 1043b495f2bb749b828499135743b9ddec46e34fda8Pete Popov struct au1100fb_regs* regs; /* Registers memory map */ 1053b495f2bb749b828499135743b9ddec46e34fda8Pete Popov size_t regs_len; 1063b495f2bb749b828499135743b9ddec46e34fda8Pete Popov unsigned int regs_phys; 1073b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 1083b495f2bb749b828499135743b9ddec46e34fda8Pete Popov unsigned char* fb_mem; /* FrameBuffer memory map */ 1093b495f2bb749b828499135743b9ddec46e34fda8Pete Popov size_t fb_len; 1103b495f2bb749b828499135743b9ddec46e34fda8Pete Popov dma_addr_t fb_phys; 111d121c3f3cedb84601ee4839d6a6c33d1e9240cc9Manuel Lauss int panel_idx; 1126b1889c14b4606b7a1d0e08d52664b704bbfe65fManuel Lauss struct clk *lcdclk; 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1153b495f2bb749b828499135743b9ddec46e34fda8Pete Popov/********************************************************************/ 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1173b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_CONTROL (AU1100_LCD_BASE + 0x0) 1183b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBB_BIT 21 1193b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT) 1203b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT) 1213b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT) 1223b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT) 1233b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT) 1243b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBPPF_BIT 18 1253b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT) 1263b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT) 1273b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT) 1283b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT) 1293b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT) 1303b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT) 1313b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_WP (1<<17) 1323b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_WD (1<<16) 1333b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_C (1<<15) 1343b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SM_BIT 13 1353b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT) 1363b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT) 1373b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT) 1383b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT) 1393b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT) 1403b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_DB (1<<12) 1413b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_CCO (1<<11) 1423b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_DP (1<<10) 1433b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_PO_BIT 8 1443b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT) 1453b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT) 1463b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT) 1473b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT) 1483b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT) 1493b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_MPI (1<<7) 1503b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_PT (1<<6) 1513b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_PC (1<<5) 1523b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_BPP_BIT 1 1533b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT) 1543b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT) 1553b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT) 1563b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT) 1573b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT) 1583b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT) 1593b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT) 1603b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CONTROL_GO (1<<0) 1613b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 1623b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4) 1633b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_INTENABLE (AU1100_LCD_BASE + 0x8) 1643b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_INT_SD (1<<7) 1653b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_INT_OF (1<<6) 1663b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_INT_UF (1<<5) 1673b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_INT_SA (1<<3) 1683b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_INT_SS (1<<2) 1693b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_INT_S1 (1<<1) 1703b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_INT_S0 (1<<0) 1713b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 1723b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC) 1733b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HN2_BIT 24 1743b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT) 1753b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK) 1763b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HN1_BIT 16 1773b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT) 1783b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK) 1793b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HPW_BIT 10 1803b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT) 1813b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK) 1823b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_PPL_BIT 0 1833b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT) 1843b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK) 1853b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 1863b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10) 1873b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VN2_BIT 24 1883b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT) 1893b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK) 1903b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VN1_BIT 16 1913b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT) 1923b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK) 1933b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VPW_BIT 10 1943b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT) 1953b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK) 1963b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_LPP_BIT 0 1973b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT) 1983b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK) 1993b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2003b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14) 2013b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_IB (1<<18) 2023b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_IC (1<<17) 2033b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_IH (1<<16) 2043b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_IV (1<<15) 2053b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_BF_BIT 10 2063b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT) 2073b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK) 2083b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_PCD_BIT 0 2093b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT) 2103b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK) 2113b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2123b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18) 2133b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C) 2143b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_DMA_SA_BIT 5 2153b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT) 2163b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK) 2173b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2183b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_WORDS (AU1100_LCD_BASE + 0x20) 2193b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_WRD_WRDS_BIT 0 2203b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT) 2213b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK) 2223b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2233b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_PWMDIV (AU1100_LCD_BASE + 0x24) 2243b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMDIV_EN (1<<12) 2253b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMDIV_PWMDIV_BIT 0 2263b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT) 2273b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK) 2283b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2293b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_PWMHI (AU1100_LCD_BASE + 0x28) 2303b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMHI_PWMHI1_BIT 12 2313b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT) 2323b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK) 2333b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMHI_PWMHI0_BIT 0 2343b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT) 2353b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK) 2363b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2373b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400) 2383b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_MONO_MI_BIT 0 2393b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT) 2403b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK) 2413b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2423b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_RI_BIT 8 2433b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT) 2443b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK) 2453b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_GI_BIT 4 2463b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT) 2473b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK) 2483b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_BI_BIT 0 2493b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT) 2503b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK) 2513b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2523b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_TFT_DC_BIT 0 2533b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT) 2543b495f2bb749b828499135743b9ddec46e34fda8Pete Popov #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK) 2553b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2563b495f2bb749b828499135743b9ddec46e34fda8Pete Popov/********************************************************************/ 2573b495f2bb749b828499135743b9ddec46e34fda8Pete Popov 2583b495f2bb749b828499135743b9ddec46e34fda8Pete Popov/* List of panels known to work with the AU1100 LCD controller. 2593b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * To add a new panel, enter the same specifications as the 2603b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * Generic_TFT one, and MAKE SURE that it doesn't conflicts 2613b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * with the controller restrictions. Restrictions are: 2623b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * 2633b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * STN color panels: max_bpp <= 12 2643b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * STN mono panels: max_bpp <= 4 2653b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * TFT panels: max_bpp <= 16 2663b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * max_xres <= 800 2673b495f2bb749b828499135743b9ddec46e34fda8Pete Popov * max_yres <= 600 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2693b495f2bb749b828499135743b9ddec46e34fda8Pete Popovstatic struct au1100fb_panel known_lcd_panels[] = 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2713b495f2bb749b828499135743b9ddec46e34fda8Pete Popov /* 800x600x16bpp CRT */ 2723b495f2bb749b828499135743b9ddec46e34fda8Pete Popov [0] = { 2733b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .name = "CRT_800x600_16", 2743b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .xres = 800, 2753b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .yres = 600, 2763b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .bpp = 16, 2773b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .control_base = 0x0004886A | 2783b495f2bb749b828499135743b9ddec46e34fda8Pete Popov LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF | 27903ae4e0ccc10ad2d8b7f421fbbeac4fe44b806fbFreddy Spierenburg LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4, 2803b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .clkcontrol_base = 0x00020000, 2813b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .horztiming = 0x005aff1f, 2823b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .verttiming = 0x16000e57, 2833b495f2bb749b828499135743b9ddec46e34fda8Pete Popov }, 2843b495f2bb749b828499135743b9ddec46e34fda8Pete Popov /* just the standard LCD */ 2853b495f2bb749b828499135743b9ddec46e34fda8Pete Popov [1] = { 2863b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .name = "WWPC LCD", 2873b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .xres = 240, 2883b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .yres = 320, 2893b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .bpp = 16, 2903b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .control_base = 0x0006806A, 2913b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .horztiming = 0x0A1010EF, 2923b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .verttiming = 0x0301013F, 2933b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .clkcontrol_base = 0x00018001, 2943b495f2bb749b828499135743b9ddec46e34fda8Pete Popov }, 2953b495f2bb749b828499135743b9ddec46e34fda8Pete Popov /* Sharp 320x240 TFT panel */ 2963b495f2bb749b828499135743b9ddec46e34fda8Pete Popov [2] = { 2973b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .name = "Sharp_LQ038Q5DR01", 2983b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .xres = 320, 2993b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .yres = 240, 3003b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .bpp = 16, 3013b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .control_base = 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ( LCD_CONTROL_SBPPF_565 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_CONTROL_C 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_CONTROL_SM_0 3053b495f2bb749b828499135743b9ddec46e34fda8Pete Popov | LCD_CONTROL_DEFAULT_PO 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_CONTROL_PT 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_CONTROL_PC 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_CONTROL_BPP_16 ), 3093b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .horztiming = 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ( LCD_HORZTIMING_HN2_N(8) 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_HORZTIMING_HN1_N(60) 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_HORZTIMING_HPW_N(12) 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_HORZTIMING_PPL_N(320) ), 3143b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .verttiming = 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ( LCD_VERTTIMING_VN2_N(5) 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_VERTTIMING_VN1_N(17) 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_VERTTIMING_VPW_N(1) 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | LCD_VERTTIMING_LPP_N(240) ), 3193b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1), 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3223b495f2bb749b828499135743b9ddec46e34fda8Pete Popov /* Hitachi SP14Q005 and possibly others */ 3233b495f2bb749b828499135743b9ddec46e34fda8Pete Popov [3] = { 3243b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .name = "Hitachi_SP14Qxxx", 3253b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .xres = 320, 3263b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .yres = 240, 3273b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .bpp = 4, 3283b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .control_base = 3293b495f2bb749b828499135743b9ddec46e34fda8Pete Popov ( LCD_CONTROL_C 3303b495f2bb749b828499135743b9ddec46e34fda8Pete Popov | LCD_CONTROL_BPP_4 ), 3313b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .horztiming = 3323b495f2bb749b828499135743b9ddec46e34fda8Pete Popov ( LCD_HORZTIMING_HN2_N(1) 3333b495f2bb749b828499135743b9ddec46e34fda8Pete Popov | LCD_HORZTIMING_HN1_N(1) 3343b495f2bb749b828499135743b9ddec46e34fda8Pete Popov | LCD_HORZTIMING_HPW_N(1) 3353b495f2bb749b828499135743b9ddec46e34fda8Pete Popov | LCD_HORZTIMING_PPL_N(320) ), 3363b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .verttiming = 3373b495f2bb749b828499135743b9ddec46e34fda8Pete Popov ( LCD_VERTTIMING_VN2_N(1) 3383b495f2bb749b828499135743b9ddec46e34fda8Pete Popov | LCD_VERTTIMING_VN1_N(1) 3393b495f2bb749b828499135743b9ddec46e34fda8Pete Popov | LCD_VERTTIMING_VPW_N(1) 3403b495f2bb749b828499135743b9ddec46e34fda8Pete Popov | LCD_VERTTIMING_LPP_N(240) ), 3413b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4), 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3443b495f2bb749b828499135743b9ddec46e34fda8Pete Popov /* Generic 640x480 TFT panel */ 3453b495f2bb749b828499135743b9ddec46e34fda8Pete Popov [4] = { 3463b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .name = "TFT_640x480_16", 3473b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .xres = 640, 3483b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .yres = 480, 3493b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .bpp = 16, 3503b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO, 3513b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .horztiming = 0x3434d67f, 3523b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .verttiming = 0x0e0e39df, 3533b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1), 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3563b495f2bb749b828499135743b9ddec46e34fda8Pete Popov /* Pb1100 LCDB 640x480 PrimeView TFT panel */ 3573b495f2bb749b828499135743b9ddec46e34fda8Pete Popov [5] = { 3583b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .name = "PrimeView_640x480_16", 3593b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .xres = 640, 3603b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .yres = 480, 3613b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .bpp = 16, 3623b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO, 3633b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .horztiming = 0x0e4bfe7f, 3643b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .verttiming = 0x210805df, 3653b495f2bb749b828499135743b9ddec46e34fda8Pete Popov .clkcontrol_base = 0x00038001, 3661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 3673b495f2bb749b828499135743b9ddec46e34fda8Pete Popov}; 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3693b495f2bb749b828499135743b9ddec46e34fda8Pete Popov/********************************************************************/ 3701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3713b495f2bb749b828499135743b9ddec46e34fda8Pete Popov/* Inline helpers */ 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3733b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP) 3743b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT) 3753b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC) 3763b495f2bb749b828499135743b9ddec46e34fda8Pete Popov#define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO) 3771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* _AU1100LCD_H */ 379