11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com> 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Contributors (thanks, all!) 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * David Eger: 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Overhaul for Linux 2.6 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Jeff Rugen: 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Major contributions; Motorola PowerStack (PPC and PCI) support, 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * GD54xx, 1280x1024 mode support, change MCLK based on VCLK. 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Geert Uytterhoeven: 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Excellent code review. 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Lars Hecking: 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Amiga updates and testing. 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Original cirrusfb author: Frank Neumann 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Based on retz3fb.c and cirrusfb.c: 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 1997 Jes Sorensen 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 1996 Frank Neumann 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *************************************************************** 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Format this code with GNU indent '-kr -i8 -pcs' options. 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This file is subject to the terms and conditions of the GNU General Public 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * License. See the file COPYING in the main directory of this archive 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * for more details. 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/module.h> 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/kernel.h> 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/errno.h> 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/string.h> 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/mm.h> 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/delay.h> 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/fb.h> 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/init.h> 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/pgtable.h> 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/zorro.h> 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_PCI 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/pci.h> 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_AMIGA 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <asm/amigahw.h> 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 570ff1edeef222ebed71499135a8cc259b107d85fdKrzysztof Helt#include <video/vga.h> 580ff1edeef222ebed71499135a8cc259b107d85fdKrzysztof Helt#include <video/cirrus.h> 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/***************************************************************** 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * debugging and utility macros 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* disable runtime assertions? */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* #define CIRRUSFB_NDEBUG */ 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* debugging assertions */ 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef CIRRUSFB_NDEBUG 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define assert(expr) \ 728503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (!(expr)) { \ 738503df65976d0f845f49e8debff55c031635754eKrzysztof Helt printk("Assertion failed! %s,%s,%s,line=%d\n", \ 745ae121705bed9ea7425daef4d7d29038f7312f3fHarvey Harrison #expr, __FILE__, __func__, __LINE__); \ 758503df65976d0f845f49e8debff55c031635754eKrzysztof Helt } 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#else 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define assert(expr) 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 808503df65976d0f845f49e8debff55c031635754eKrzysztof Helt#define MB_ (1024 * 1024) 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/***************************************************************** 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * chipset information 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* board types */ 897345de32df7ef0ab49eaa88cad1297d8572a6757Krzysztof Heltenum cirrus_board { 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds BT_NONE = 0, 917cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt BT_SD64, /* GD5434 */ 927cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt BT_PICCOLO, /* GD5426 */ 937cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt BT_PICASSO, /* GD5426 or GD5428 */ 947cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt BT_SPECTRUM, /* GD5426 or GD5428 */ 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds BT_PICASSO4, /* GD5446 */ 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds BT_ALPINE, /* GD543x/4x */ 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds BT_GD5480, 9878d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt BT_LAGUNA, /* GD5462/64 */ 9978d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt BT_LAGUNAB, /* GD5465 */ 1007345de32df7ef0ab49eaa88cad1297d8572a6757Krzysztof Helt}; 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * per-board-type information, used for enumerating and abstracting 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * chip-specific information 1057345de32df7ef0ab49eaa88cad1297d8572a6757Krzysztof Helt * NOTE: MUST be in the same order as enum cirrus_board in order to 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * use direct indexing on this array 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * NOTE: '__initdata' cannot be used as some of this info 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * is required at runtime. Maybe separate into an init-only and 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * a run-time table? 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic const struct cirrusfb_board_info_rec { 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds char *name; /* ASCII name of chipset */ 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds long maxclock[5]; /* maximum video clock */ 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */ 115c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson bool init_sr07 : 1; /* init SR07 during init_vgachip() */ 116c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson bool init_sr1f : 1; /* write SR1F during init_vgachip() */ 1178503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* construct bit 19 of screen start address */ 1188503df65976d0f845f49e8debff55c031635754eKrzysztof Helt bool scrn_start_bit19 : 1; 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* initial SR07 value, then for each mode */ 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char sr07; 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char sr07_1bpp; 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char sr07_1bpp_mux; 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char sr07_8bpp; 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char sr07_8bpp_mux; 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char sr1f; /* SR1F VGA initial register value */ 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} cirrusfb_board_info[] = { 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds [BT_SD64] = { 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "CL SD64", 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .maxclock = { 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* guess */ 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* the SD64/P4 have a higher max. videoclock */ 13475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 135100, 135100, 85500, 85500, 0 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 136c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr07 = true, 137c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr1f = true, 138c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .scrn_start_bit19 = true, 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07 = 0xF0, 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_1bpp = 0xF0, 141df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt .sr07_1bpp_mux = 0xF6, 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_8bpp = 0xF1, 143df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt .sr07_8bpp_mux = 0xF7, 1448f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt .sr1f = 0x1E 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds [BT_PICCOLO] = { 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "CL Piccolo", 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .maxclock = { 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* guess */ 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 90000, 90000, 90000, 90000, 90000 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 152c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr07 = true, 153c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr1f = true, 154c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .scrn_start_bit19 = false, 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07 = 0x80, 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_1bpp = 0x80, 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_8bpp = 0x81, 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr1f = 0x22 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds [BT_PICASSO] = { 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "CL Picasso", 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .maxclock = { 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* guess */ 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 90000, 90000, 90000, 90000, 90000 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 166c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr07 = true, 167c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr1f = true, 168c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .scrn_start_bit19 = false, 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07 = 0x20, 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_1bpp = 0x20, 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_8bpp = 0x21, 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr1f = 0x22 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds [BT_SPECTRUM] = { 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "CL Spectrum", 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .maxclock = { 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* guess */ 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 90000, 90000, 90000, 90000, 90000 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 180c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr07 = true, 181c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr1f = true, 182c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .scrn_start_bit19 = false, 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07 = 0x80, 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_1bpp = 0x80, 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_8bpp = 0x81, 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr1f = 0x22 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds [BT_PICASSO4] = { 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "CL Picasso4", 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .maxclock = { 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 135100, 135100, 85500, 85500, 0 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 193c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr07 = true, 194c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr1f = false, 195c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .scrn_start_bit19 = true, 196527410ff7fc5d45fe41523c0ba061113dea22017Krzysztof Helt .sr07 = 0xA0, 197527410ff7fc5d45fe41523c0ba061113dea22017Krzysztof Helt .sr07_1bpp = 0xA0, 198527410ff7fc5d45fe41523c0ba061113dea22017Krzysztof Helt .sr07_1bpp_mux = 0xA6, 199527410ff7fc5d45fe41523c0ba061113dea22017Krzysztof Helt .sr07_8bpp = 0xA1, 200527410ff7fc5d45fe41523c0ba061113dea22017Krzysztof Helt .sr07_8bpp_mux = 0xA7, 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr1f = 0 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds [BT_ALPINE] = { 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "CL Alpine", 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .maxclock = { 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* for the GD5430. GD5446 can do more... */ 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 85500, 85500, 50000, 28500, 0 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 209c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr07 = true, 210c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr1f = true, 211c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .scrn_start_bit19 = true, 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07 = 0xA0, 213527410ff7fc5d45fe41523c0ba061113dea22017Krzysztof Helt .sr07_1bpp = 0xA0, 214527410ff7fc5d45fe41523c0ba061113dea22017Krzysztof Helt .sr07_1bpp_mux = 0xA6, 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_8bpp = 0xA1, 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_8bpp_mux = 0xA7, 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr1f = 0x1C 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds [BT_GD5480] = { 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "CL GD5480", 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .maxclock = { 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 135100, 200000, 200000, 135100, 135100 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 224c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr07 = true, 225c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr1f = true, 226c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .scrn_start_bit19 = true, 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07 = 0x10, 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_1bpp = 0x11, 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr07_8bpp = 0x11, 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .sr1f = 0x1C 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds [BT_LAGUNA] = { 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "CL Laguna", 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .maxclock = { 23578d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt /* taken from X11 code */ 23678d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt 170000, 170000, 170000, 170000, 135100, 23778d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt }, 23878d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt .init_sr07 = false, 23978d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt .init_sr1f = false, 24078d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt .scrn_start_bit19 = true, 24178d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt }, 24278d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt [BT_LAGUNAB] = { 24378d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt .name = "CL Laguna AGP", 24478d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt .maxclock = { 24578d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt /* taken from X11 code */ 24678d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt 170000, 250000, 170000, 170000, 135100, 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 248c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr07 = false, 249c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .init_sr1f = false, 250c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson .scrn_start_bit19 = true, 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_PCI 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CHIP(id, btype) \ 2564153812fc10ea91cb1a7b6ea4f4337dd211c1ef7Grant Coady { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) } 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic struct pci_device_id cirrusfb_pci_table[] = { 2598503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE), 260df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64), 261df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64), 2628503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */ 2638503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE), 2648503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE), 2658503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */ 2668503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */ 2678503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */ 2688503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */ 26978d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/ 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 0, } 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_DEVICE_TABLE(pci, cirrusfb_pci_table); 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#undef CHIP 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CONFIG_PCI */ 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO 2770e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoevenstruct zorrocl { 2780e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven enum cirrus_board type; /* Board type */ 2790e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven u32 regoffset; /* Offset of registers in first Zorro device */ 2800e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven u32 ramsize; /* Size of video RAM in first Zorro device */ 2810e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven /* If zero, use autoprobe on RAM device */ 2820e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven u32 ramoffset; /* Offset of video RAM in first Zorro device */ 2830e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven zorro_id ramid; /* Zorro ID of RAM device */ 28417bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven zorro_id ramid2; /* Zorro ID of optional second RAM device */ 2850e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven}; 2860e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 28748c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic const struct zorrocl zcl_sd64 = { 2880e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .type = BT_SD64, 2890e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .ramid = ZORRO_PROD_HELFRICH_SD64_RAM, 2900e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven}; 2910e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 29248c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic const struct zorrocl zcl_piccolo = { 2930e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .type = BT_PICCOLO, 2940e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .ramid = ZORRO_PROD_HELFRICH_PICCOLO_RAM, 2950e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven}; 2960e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 29748c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic const struct zorrocl zcl_picasso = { 2980e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .type = BT_PICASSO, 2990e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM, 3000e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven}; 3010e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 30248c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic const struct zorrocl zcl_spectrum = { 3030e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .type = BT_SPECTRUM, 3040e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .ramid = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM, 3050e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven}; 3060e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 30748c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic const struct zorrocl zcl_picasso4_z3 = { 3080e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .type = BT_PICASSO4, 3090e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .regoffset = 0x00600000, 3100e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .ramsize = 4 * MB_, 311e78bb882bf318bb41e17b33729cca3bdd26b42a0Geert Uytterhoeven .ramoffset = 0x01000000, /* 0x02000000 for 64 MiB boards */ 3120e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven}; 3130e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 31448c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic const struct zorrocl zcl_picasso4_z2 = { 31517bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven .type = BT_PICASSO4, 31617bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven .regoffset = 0x10000, 31717bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1, 31817bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven .ramid2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2, 31917bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven}; 32017bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven 3210e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 32248c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic const struct zorro_device_id cirrusfb_zorro_table[] = { 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 3240e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .id = ZORRO_PROD_HELFRICH_SD64_REG, 3250e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .driver_data = (unsigned long)&zcl_sd64, 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, { 3270e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .id = ZORRO_PROD_HELFRICH_PICCOLO_REG, 3280e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .driver_data = (unsigned long)&zcl_piccolo, 3291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, { 3300e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG, 3310e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .driver_data = (unsigned long)&zcl_picasso, 3321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, { 3330e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG, 3340e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .driver_data = (unsigned long)&zcl_spectrum, 3351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, { 3361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3, 3370e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven .driver_data = (unsigned long)&zcl_picasso4_z3, 33817bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven }, { 33917bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG, 34017bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven .driver_data = (unsigned long)&zcl_picasso4_z2, 3411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds }, 3421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds { 0 } 3431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 344bf54a2b3c0dbf76136f00ff785bf6d8f6291311dGeert UytterhoevenMODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table); 3451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CONFIG_ZORRO */ 3461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CIRRUSFB_DEBUG 3487345de32df7ef0ab49eaa88cad1297d8572a6757Krzysztof Heltenum cirrusfb_dbg_reg_class { 3498503df65976d0f845f49e8debff55c031635754eKrzysztof Helt CRT, 3508503df65976d0f845f49e8debff55c031635754eKrzysztof Helt SEQ 3517345de32df7ef0ab49eaa88cad1297d8572a6757Krzysztof Helt}; 3528503df65976d0f845f49e8debff55c031635754eKrzysztof Helt#endif /* CIRRUSFB_DEBUG */ 3531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* info about board */ 3551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstruct cirrusfb_info { 3561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 __iomem *regbase; 3576e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt u8 __iomem *laguna_mmio; 3587345de32df7ef0ab49eaa88cad1297d8572a6757Krzysztof Helt enum cirrus_board btype; 3591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char SFR; /* Shadow of special function register */ 3601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 36148c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt int multiplexing; 362df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt int doubleVCLK; 3631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int blank_mode; 36464beab14f53790e59a4e0a9ef1d752c12ad54a62Krzysztof Helt u32 pseudo_palette[16]; 3651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3669199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt void (*unmap)(struct fb_info *info); 3671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 3681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 36948c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic bool noaccel; 37048c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic char *mode_option = "640x480@60"; 3711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/****************************************************************************/ 3731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/**** BEGIN PROTOTYPES ******************************************************/ 3741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*--- Interface used by the world ------------------------------------------*/ 3768503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int cirrusfb_pan_display(struct fb_var_screeninfo *var, 3778503df65976d0f845f49e8debff55c031635754eKrzysztof Helt struct fb_info *info); 3781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*--- Internal routines ----------------------------------------------------*/ 3809199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Heltstatic void init_vgachip(struct fb_info *info); 3818503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void switch_monitor(struct cirrusfb_info *cinfo, int on); 3828503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WGen(const struct cirrusfb_info *cinfo, 3838503df65976d0f845f49e8debff55c031635754eKrzysztof Helt int regnum, unsigned char val); 3848503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum); 3858503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void AttrOn(const struct cirrusfb_info *cinfo); 3868503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WHDR(const struct cirrusfb_info *cinfo, unsigned char val); 3878503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WSFR(struct cirrusfb_info *cinfo, unsigned char val); 3888503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WSFR2(struct cirrusfb_info *cinfo, unsigned char val); 3898503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, 3908503df65976d0f845f49e8debff55c031635754eKrzysztof Helt unsigned char red, unsigned char green, unsigned char blue); 3911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if 0 3928503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, 3938503df65976d0f845f49e8debff55c031635754eKrzysztof Helt unsigned char *red, unsigned char *green, 3948503df65976d0f845f49e8debff55c031635754eKrzysztof Helt unsigned char *blue); 3951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 3968503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void cirrusfb_WaitBLT(u8 __iomem *regbase); 3978503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel, 3988503df65976d0f845f49e8debff55c031635754eKrzysztof Helt u_short curx, u_short cury, 3998503df65976d0f845f49e8debff55c031635754eKrzysztof Helt u_short destx, u_short desty, 4008503df65976d0f845f49e8debff55c031635754eKrzysztof Helt u_short width, u_short height, 4018503df65976d0f845f49e8debff55c031635754eKrzysztof Helt u_short line_length); 4028503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel, 4038503df65976d0f845f49e8debff55c031635754eKrzysztof Helt u_short x, u_short y, 4048503df65976d0f845f49e8debff55c031635754eKrzysztof Helt u_short width, u_short height, 4059e848062533207130667f6eaa748549367ccbedfKrzysztof Helt u32 fg_color, u32 bg_color, 4069e848062533207130667f6eaa748549367ccbedfKrzysztof Helt u_short line_length, u_char blitmode); 4078503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 408dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Heltstatic void bestclock(long freq, int *nom, int *den, int *div); 4091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CIRRUSFB_DEBUG 41175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Heltstatic void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase); 41275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Heltstatic void cirrusfb_dbg_print_regs(struct fb_info *info, 41375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt caddr_t regbase, 4147345de32df7ef0ab49eaa88cad1297d8572a6757Krzysztof Helt enum cirrusfb_dbg_reg_class reg_class, ...); 4151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CIRRUSFB_DEBUG */ 4161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** END PROTOTYPES ********************************************************/ 4181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*****************************************************************************/ 4191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** BEGIN Interface Used by the World ***************************************/ 4201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 42178d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Heltstatic inline int is_laguna(const struct cirrusfb_info *cinfo) 42278d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt{ 42378d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB; 42478d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt} 42578d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt 4268503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int opencount; 4271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*--- Open /dev/fbx ---------------------------------------------------------*/ 4298503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int cirrusfb_open(struct fb_info *info, int user) 4301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 4311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (opencount++ == 0) 4328503df65976d0f845f49e8debff55c031635754eKrzysztof Helt switch_monitor(info->par, 1); 4331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 4341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*--- Close /dev/fbx --------------------------------------------------------*/ 4378503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int cirrusfb_release(struct fb_info *info, int user) 4381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 4391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (--opencount == 0) 4408503df65976d0f845f49e8debff55c031635754eKrzysztof Helt switch_monitor(info->par, 0); 4411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 4421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/**** END Interface used by the World *************************************/ 4451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/****************************************************************************/ 4461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/**** BEGIN Hardware specific Routines **************************************/ 4471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 448486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt/* Check if the MCLK is not a better clock source */ 44975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Heltstatic int cirrusfb_check_mclk(struct fb_info *info, long freq) 4501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 45175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt struct cirrusfb_info *cinfo = info->par; 452486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; 4531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 454486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt /* Read MCLK value */ 455486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt mclk = (14318 * mclk) >> 3; 45675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk); 4571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 4581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Determine if we should use MCLK instead of VCLK, and if so, what we 459486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt * should divide it by to get VCLK 460486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt */ 461486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt 462486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt if (abs(freq - mclk) < 250) { 46375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "Using VCLK = MCLK\n"); 464486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt return 1; 465486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt } else if (abs(freq - (mclk / 2)) < 250) { 46675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "Using VCLK = MCLK/2\n"); 467486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt return 2; 4681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 4691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 470486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt return 0; 4711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 4721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 47399a4584752bb41330342a427d014482525de7433Krzysztof Heltstatic int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var, 47499a4584752bb41330342a427d014482525de7433Krzysztof Helt struct fb_info *info) 47599a4584752bb41330342a427d014482525de7433Krzysztof Helt{ 47699a4584752bb41330342a427d014482525de7433Krzysztof Helt long freq; 47799a4584752bb41330342a427d014482525de7433Krzysztof Helt long maxclock; 47899a4584752bb41330342a427d014482525de7433Krzysztof Helt struct cirrusfb_info *cinfo = info->par; 47999a4584752bb41330342a427d014482525de7433Krzysztof Helt unsigned maxclockidx = var->bits_per_pixel >> 3; 48099a4584752bb41330342a427d014482525de7433Krzysztof Helt 48199a4584752bb41330342a427d014482525de7433Krzysztof Helt /* convert from ps to kHz */ 48299a4584752bb41330342a427d014482525de7433Krzysztof Helt freq = PICOS2KHZ(var->pixclock); 48399a4584752bb41330342a427d014482525de7433Krzysztof Helt 48499a4584752bb41330342a427d014482525de7433Krzysztof Helt dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq); 48599a4584752bb41330342a427d014482525de7433Krzysztof Helt 48699a4584752bb41330342a427d014482525de7433Krzysztof Helt maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx]; 48799a4584752bb41330342a427d014482525de7433Krzysztof Helt cinfo->multiplexing = 0; 48899a4584752bb41330342a427d014482525de7433Krzysztof Helt 48999a4584752bb41330342a427d014482525de7433Krzysztof Helt /* If the frequency is greater than we can support, we might be able 49099a4584752bb41330342a427d014482525de7433Krzysztof Helt * to use multiplexing for the video mode */ 49199a4584752bb41330342a427d014482525de7433Krzysztof Helt if (freq > maxclock) { 492dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt dev_err(info->device, 493dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt "Frequency greater than maxclock (%ld kHz)\n", 494dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt maxclock); 495dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt return -EINVAL; 496dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt } 497dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt /* 498dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt * Additional constraint: 8bpp uses DAC clock doubling to allow maximum 499dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt * pixel clock 500dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt */ 501dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt if (var->bits_per_pixel == 8) { 50299a4584752bb41330342a427d014482525de7433Krzysztof Helt switch (cinfo->btype) { 50399a4584752bb41330342a427d014482525de7433Krzysztof Helt case BT_ALPINE: 5048f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt case BT_SD64: 505dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt case BT_PICASSO4: 506dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt if (freq > 85500) 507dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt cinfo->multiplexing = 1; 508dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt break; 50999a4584752bb41330342a427d014482525de7433Krzysztof Helt case BT_GD5480: 510dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt if (freq > 135100) 511dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt cinfo->multiplexing = 1; 51299a4584752bb41330342a427d014482525de7433Krzysztof Helt break; 51399a4584752bb41330342a427d014482525de7433Krzysztof Helt 51499a4584752bb41330342a427d014482525de7433Krzysztof Helt default: 5158f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt break; 51699a4584752bb41330342a427d014482525de7433Krzysztof Helt } 51799a4584752bb41330342a427d014482525de7433Krzysztof Helt } 518df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt 519df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt /* If we have a 1MB 5434, we need to put ourselves in a mode where 52099a4584752bb41330342a427d014482525de7433Krzysztof Helt * the VCLK is double the pixel clock. */ 521df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt cinfo->doubleVCLK = 0; 522df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ && 523df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt var->bits_per_pixel == 16) { 524df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt cinfo->doubleVCLK = 1; 52599a4584752bb41330342a427d014482525de7433Krzysztof Helt } 526df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt 52799a4584752bb41330342a427d014482525de7433Krzysztof Helt return 0; 52899a4584752bb41330342a427d014482525de7433Krzysztof Helt} 52999a4584752bb41330342a427d014482525de7433Krzysztof Helt 5301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic int cirrusfb_check_var(struct fb_var_screeninfo *var, 5311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_info *info) 5321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 53309a2910e54646f7a334702fbafa7a6129dc072e6Krzysztof Helt int yres; 53409a2910e54646f7a334702fbafa7a6129dc072e6Krzysztof Helt /* memory size in pixels */ 53509a2910e54646f7a334702fbafa7a6129dc072e6Krzysztof Helt unsigned pixels = info->screen_size * 8 / var->bits_per_pixel; 536614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt struct cirrusfb_info *cinfo = info->par; 5371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (var->bits_per_pixel) { 539060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt case 1: 5401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->red.offset = 0; 5411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->red.length = 1; 542060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt var->green = var->red; 543060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt var->blue = var->red; 5441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case 8: 5471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->red.offset = 0; 54899a4584752bb41330342a427d014482525de7433Krzysztof Helt var->red.length = 8; 549060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt var->green = var->red; 550060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt var->blue = var->red; 5511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case 16: 554933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle var->red.offset = 11; 555933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle var->green.offset = 5; 556933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle var->blue.offset = 0; 5571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->red.length = 5; 558c4dec3962d6bff26010fcfc61500c1241469a6e0Krzysztof Helt var->green.length = 6; 5591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->blue.length = 5; 5601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5627cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt case 24: 563933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle var->red.offset = 16; 564933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle var->green.offset = 8; 565933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle var->blue.offset = 0; 5661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->red.length = 8; 5671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->green.length = 8; 5681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->blue.length = 8; 5691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 5701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 5711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 57275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, 57375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt "Unsupported bpp size: %d\n", var->bits_per_pixel); 5740efb2a03af7eddadb4d0db5f855b1614ba9b0a00Krzysztof Helt return -EINVAL; 5751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 5761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 57775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt if (var->xres_virtual < var->xres) 57875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt var->xres_virtual = var->xres; 57975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt /* use highest possible virtual resolution */ 58075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt if (var->yres_virtual == -1) { 58175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt var->yres_virtual = pixels / var->xres_virtual; 58275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 58375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_info(info->device, 58475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt "virtual resolution set to maximum of %dx%d\n", 58575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt var->xres_virtual, var->yres_virtual); 58675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt } 58775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt if (var->yres_virtual < var->yres) 58875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt var->yres_virtual = var->yres; 58975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 59075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt if (var->xres_virtual * var->yres_virtual > pixels) { 59175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_err(info->device, "mode %dx%dx%d rejected... " 59275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt "virtual resolution too high to fit into video memory!\n", 59375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt var->xres_virtual, var->yres_virtual, 59475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt var->bits_per_pixel); 59575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt return -EINVAL; 59675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt } 59775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 59875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt /* truncate xoffset and yoffset to maximum if too high */ 59975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt if (var->xoffset > var->xres_virtual - var->xres) 60075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt var->xoffset = var->xres_virtual - var->xres - 1; 60175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt if (var->yoffset > var->yres_virtual - var->yres) 60275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt var->yoffset = var->yres_virtual - var->yres - 1; 60375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 6041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->red.msb_right = 6051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->green.msb_right = 6061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->blue.msb_right = 6071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->transp.offset = 6081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->transp.length = 6091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->transp.msb_right = 0; 6101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds yres = var->yres; 6121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->vmode & FB_VMODE_DOUBLE) 6131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds yres *= 2; 6141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else if (var->vmode & FB_VMODE_INTERLACED) 6151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds yres = (yres + 1) / 2; 6161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (yres >= 1280) { 61875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_err(info->device, "ERROR: VerticalTotal >= 1280; " 6198503df65976d0f845f49e8debff55c031635754eKrzysztof Helt "special treatment required! (TODO)\n"); 6201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return -EINVAL; 6211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 6221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 62399a4584752bb41330342a427d014482525de7433Krzysztof Helt if (cirrusfb_check_pixclock(var, info)) 62499a4584752bb41330342a427d014482525de7433Krzysztof Helt return -EINVAL; 6251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 626614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt if (!is_laguna(cinfo)) 627614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt var->accel_flags = FB_ACCELF_TEXT; 628614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt 6291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 6301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 6311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 63275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Heltstatic void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div) 6331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 63475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt struct cirrusfb_info *cinfo = info->par; 635486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt unsigned char old1f, old1e; 63675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 6378503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(cinfo != NULL); 638486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; 639486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt 640486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt if (div) { 64175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "Set %s as pixclock source.\n", 64275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt (div == 2) ? "MCLK/2" : "MCLK"); 643486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt old1f |= 0x40; 644486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; 645486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt if (div == 2) 646486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt old1e |= 1; 6471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 648486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); 6491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 650486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR1F, old1f); 6511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 6521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/************************************************************************* 6541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cirrusfb_set_par_foo() 6551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds actually writes the values for a new video mode into the hardware, 6571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds**************************************************************************/ 6588503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int cirrusfb_set_par_foo(struct fb_info *info) 6591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 6601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct cirrusfb_info *cinfo = info->par; 6611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_var_screeninfo *var = &info->var; 6621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u8 __iomem *regbase = cinfo->regbase; 6631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char tmp; 6646683e01e2c950f635a6c0e2bbc80db1b1838311fKrzysztof Helt int pitch; 6651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds const struct cirrusfb_board_info_rec *bi; 6669a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt int hdispend, hsyncstart, hsyncend, htotal; 6679a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt int yres, vdispend, vsyncstart, vsyncend, vtotal; 668dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt long freq; 669dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt int nom, den, div; 6701b48cb563d59e03dbf530174f30c0ed3b6fba513Krzysztof Helt unsigned int control = 0, format = 0, threshold = 0; 6711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 67275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "Requested mode: %dx%dx%d\n", 6731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->xres, var->yres, var->bits_per_pixel); 6741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 67599a4584752bb41330342a427d014482525de7433Krzysztof Helt switch (var->bits_per_pixel) { 67699a4584752bb41330342a427d014482525de7433Krzysztof Helt case 1: 67799a4584752bb41330342a427d014482525de7433Krzysztof Helt info->fix.line_length = var->xres_virtual / 8; 67899a4584752bb41330342a427d014482525de7433Krzysztof Helt info->fix.visual = FB_VISUAL_MONO10; 67999a4584752bb41330342a427d014482525de7433Krzysztof Helt break; 6801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 68199a4584752bb41330342a427d014482525de7433Krzysztof Helt case 8: 68299a4584752bb41330342a427d014482525de7433Krzysztof Helt info->fix.line_length = var->xres_virtual; 68399a4584752bb41330342a427d014482525de7433Krzysztof Helt info->fix.visual = FB_VISUAL_PSEUDOCOLOR; 68499a4584752bb41330342a427d014482525de7433Krzysztof Helt break; 68599a4584752bb41330342a427d014482525de7433Krzysztof Helt 68699a4584752bb41330342a427d014482525de7433Krzysztof Helt case 16: 6877cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt case 24: 68899a4584752bb41330342a427d014482525de7433Krzysztof Helt info->fix.line_length = var->xres_virtual * 68999a4584752bb41330342a427d014482525de7433Krzysztof Helt var->bits_per_pixel >> 3; 69099a4584752bb41330342a427d014482525de7433Krzysztof Helt info->fix.visual = FB_VISUAL_TRUECOLOR; 69199a4584752bb41330342a427d014482525de7433Krzysztof Helt break; 6921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 69399a4584752bb41330342a427d014482525de7433Krzysztof Helt info->fix.type = FB_TYPE_PACKED_PIXELS; 69499a4584752bb41330342a427d014482525de7433Krzysztof Helt 69599a4584752bb41330342a427d014482525de7433Krzysztof Helt init_vgachip(info); 6961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bi = &cirrusfb_board_info[cinfo->btype]; 6981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 6999a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt hsyncstart = var->xres + var->right_margin; 7009a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt hsyncend = hsyncstart + var->hsync_len; 7018636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt htotal = (hsyncend + var->left_margin) / 8; 7028636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt hdispend = var->xres / 8; 7038636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt hsyncstart = hsyncstart / 8; 7048636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt hsyncend = hsyncend / 8; 7059a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt 7068636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt vdispend = var->yres; 7078636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt vsyncstart = vdispend + var->lower_margin; 7089a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vsyncend = vsyncstart + var->vsync_len; 7099a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vtotal = vsyncend + var->upper_margin; 7109a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt 7119a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (var->vmode & FB_VMODE_DOUBLE) { 7128636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt vdispend *= 2; 7139a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vsyncstart *= 2; 7149a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vsyncend *= 2; 7159a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vtotal *= 2; 7169a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt } else if (var->vmode & FB_VMODE_INTERLACED) { 7178636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt vdispend = (vdispend + 1) / 2; 7189a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vsyncstart = (vsyncstart + 1) / 2; 7199a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vsyncend = (vsyncend + 1) / 2; 7209a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vtotal = (vtotal + 1) / 2; 7219a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt } 7228636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt yres = vdispend; 7239a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (yres >= 1024) { 7249a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vtotal /= 2; 7259a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vsyncstart /= 2; 7269a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vsyncend /= 2; 7279a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vdispend /= 2; 7289a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt } 7298636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt 7308636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt vdispend -= 1; 7318636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt vsyncstart -= 1; 7328636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt vsyncend -= 1; 7338636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt vtotal -= 2; 7348636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt 73548c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt if (cinfo->multiplexing) { 7369a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt htotal /= 2; 7379a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt hsyncstart /= 2; 7389a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt hsyncend /= 2; 7399a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt hdispend /= 2; 7409a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt } 7418636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt 7428636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt htotal -= 5; 7438636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt hdispend -= 1; 7448636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt hsyncstart += 1; 7458636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt hsyncend += 1; 7468636a9240cc93efa6b36f4cfe6253e0574f832c6Krzysztof Helt 7471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* unlock register VGA_CRTC_H_TOTAL..CRT7 */ 7488503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */ 7491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* if debugging is enabled, all parameters get output before writing */ 75175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT0: %d\n", htotal); 7529a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal); 7531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 75475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT1: %d\n", hdispend); 7559a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend); 7561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 75775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT2: %d\n", var->xres / 8); 7589a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8); 7591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7608503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* + 128: Compatible read */ 76175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32); 7628503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_H_BLANK_END, 7639a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt 128 + ((htotal + 5) % 32)); 7641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 76575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT4: %d\n", hsyncstart); 7669a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart); 7671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7689a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt tmp = hsyncend % 32; 7699a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if ((htotal + 5) & 32) 7701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp += 128; 77175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT5: %d\n", tmp); 7728503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp); 7731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 77475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff); 7759a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff); 7761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = 16; /* LineCompare bit #9 */ 7789a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (vtotal & 256) 7791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 1; 7809a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (vdispend & 256) 7811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 2; 7829a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (vsyncstart & 256) 7831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 4; 7849a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if ((vdispend + 1) & 256) 7851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 8; 7869a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (vtotal & 512) 7871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 32; 7889a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (vdispend & 512) 7891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 64; 7909a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (vsyncstart & 512) 7911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 128; 79275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT7: %d\n", tmp); 7938503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp); 7941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 7951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = 0x40; /* LineCompare bit #8 */ 7969a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if ((vdispend + 1) & 512) 7971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x20; 7981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->vmode & FB_VMODE_DOUBLE) 7991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x80; 80075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT9: %d\n", tmp); 8018503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp); 8021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 80375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff); 8049a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff); 8051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 80675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16); 8079a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32); 8081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 80975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff); 8109a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff); 8111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 81275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff); 8139a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff); 8141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 81575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff); 8169a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff); 8171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 81875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT18: 0xff\n"); 8198503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff); 8201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = 0; 8221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->vmode & FB_VMODE_INTERLACED) 8231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 1; 8249a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if ((htotal + 5) & 64) 8251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 16; 8269a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if ((htotal + 5) & 128) 8271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 32; 8289a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (vtotal & 256) 8291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 64; 8309a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (vtotal & 512) 8311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 128; 8321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 83375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CRT1a: %d\n", tmp); 8348503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, CL_CRT1A, tmp); 8351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 836dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt freq = PICOS2KHZ(var->pixclock); 837df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt if (var->bits_per_pixel == 24) 838df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) 839df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt freq *= 3; 840dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt if (cinfo->multiplexing) 841dd14f71cc62dd07b588cc6de935155e6fd3911c9Krzysztof Helt freq /= 2; 842df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt if (cinfo->doubleVCLK) 843df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt freq *= 2; 8447cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt 845dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt bestclock(freq, &nom, &den, &div); 846dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt 84775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n", 84875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt freq, nom, den, div); 84975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 8501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* set VCLK0 */ 8511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* hardware RefClock: 14.31818 MHz */ 8521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* formula: VClk = (OSC * N) / (D * (1+P)) */ 8531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */ 8541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 8558f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 || 8568f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt cinfo->btype == BT_SD64) { 857486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt /* if freq is close to mclk or mclk/2 select mclk 858486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt * as clock source 859486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt */ 86075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt int divMCLK = cirrusfb_check_mclk(info, freq); 861df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt if (divMCLK) 862486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt nom = 0; 863df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt cirrusfb_set_mclk_as_source(info, divMCLK); 864486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt } 86578d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (is_laguna(cinfo)) { 8666e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc); 8676e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); 8686e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt unsigned short tile_control; 8696e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt 87078d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (cinfo->btype == BT_LAGUNAB) { 87178d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4); 87278d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt tile_control &= ~0x80; 87378d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4); 87478d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt } 8756e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt 8766e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc); 8776e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); 8786e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt control = fb_readw(cinfo->laguna_mmio + 0x402); 8796e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt threshold = fb_readw(cinfo->laguna_mmio + 0xea); 8806e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt control &= ~0x6800; 8816e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt format = 0; 8824242a23c9e6b8e2462bb49bf78b76bfdf32158b5Krzysztof Helt threshold &= 0xffc0 & 0x3fbf; 8836e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt } 884486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt if (nom) { 885486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt tmp = den << 1; 886486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt if (div != 0) 887486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt tmp |= 1; 888486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */ 889486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt if ((cinfo->btype == BT_SD64) || 890486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt (cinfo->btype == BT_ALPINE) || 891486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt (cinfo->btype == BT_GD5480)) 892486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt tmp |= 0x80; 893486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt 89455a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt /* Laguna chipset has reversed clock registers */ 89578d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (is_laguna(cinfo)) { 89655a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt vga_wseq(regbase, CL_SEQRE, tmp); 89755a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt vga_wseq(regbase, CL_SEQR1E, nom); 89855a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt } else { 899df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt vga_wseq(regbase, CL_SEQRE, nom); 900df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt vga_wseq(regbase, CL_SEQR1E, tmp); 90155a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt } 902486ff387c0f27030a3cfb142469ba140f2d8976eKrzysztof Helt } 9031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9049a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt if (yres >= 1024) 9051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 1280x1024 */ 9068503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7); 9071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else 9081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit 9091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * address wrap, no compat. */ 9108503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3); 9111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* don't know if it would hurt to also program this if no interlaced */ 9131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* mode is used, but I feel better this way.. :-) */ 9141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->vmode & FB_VMODE_INTERLACED) 9159a85cf51fb880e24179fc45d3ee7d5ff1eb58c3aKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2); 9161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else 9178503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */ 9181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 919df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt /* adjust horizontal/vertical sync type (low/high), use VCLK3 */ 9208503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* enable display memory & CRTC I/O address for color mode */ 921df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt tmp = 0x03 | 0xc; 9221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->sync & FB_SYNC_HOR_HIGH_ACT) 9231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x40; 9241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->sync & FB_SYNC_VERT_HIGH_ACT) 9251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x80; 9268503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, VGA_MIS_W, tmp); 9271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9288503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* text cursor on and start line */ 9298503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0); 9308503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* text cursor end line */ 9318503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31); 9321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /****************************************************** 9341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 9351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 1 bpp 9361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 9371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 9381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* programming for different color depths */ 9401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->bits_per_pixel == 1) { 94175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "preparing for 1 bit deep display\n"); 9428503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */ 9431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* SR07 */ 9451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 9461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SD64: 9471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 9481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO: 9491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SPECTRUM: 9501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO4: 9511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_ALPINE: 9521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_GD5480: 9538503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 95448c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt cinfo->multiplexing ? 9551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bi->sr07_1bpp_mux : bi->sr07_1bpp); 9561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 9571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_LAGUNA: 95978d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt case BT_LAGUNAB: 9608503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 9618503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_rseq(regbase, CL_SEQR7) & ~0x01); 9621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 9631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 96575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_warn(info->device, "unknown Board\n"); 9661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 9671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 9681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Extended Sequencer Mode */ 9701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 9711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 973060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt case BT_SPECTRUM: 9748503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* evtl d0 bei 1 bit? avoid FIFO underruns..? */ 9758503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQRF, 0xb0); 9761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 9771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO: 9798503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* ## vorher d0 avoid FIFO underruns..? */ 9808503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQRF, 0xd0); 9811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 9821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9838f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt case BT_SD64: 9841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO4: 9851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_ALPINE: 9861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_GD5480: 9871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_LAGUNA: 98878d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt case BT_LAGUNAB: 9891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* do nothing */ 9901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 9911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 99375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_warn(info->device, "unknown Board\n"); 9941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 9951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 9961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 9978503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* pixel mask: pass-through for first plane */ 9988503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, VGA_PEL_MSK, 0x01); 99948c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt if (cinfo->multiplexing) 10008503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* hidden dac reg: 1280x1024 */ 10018503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WHDR(cinfo, 0x4a); 10021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else 10038503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* hidden dac: nothing */ 10048503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WHDR(cinfo, 0); 10058503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* memory mode: odd/even, ext. memory */ 10068503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06); 10078503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* plane mask: only write to first plane */ 10088503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01); 10091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 10101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /****************************************************** 10121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 10131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 8 bpp 10141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 10151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else if (var->bits_per_pixel == 8) { 101875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "preparing for 8 bit deep display\n"); 10191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 10201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SD64: 10211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 10221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO: 10231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SPECTRUM: 10241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO4: 10251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_ALPINE: 10261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_GD5480: 10278503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 102848c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt cinfo->multiplexing ? 10291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bi->sr07_8bpp_mux : bi->sr07_8bpp); 10301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 10311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_LAGUNA: 103378d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt case BT_LAGUNAB: 10348503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 10358503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_rseq(regbase, CL_SEQR7) | 0x01); 10366e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt threshold |= 0x10; 10371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 10381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 104075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_warn(info->device, "unknown Board\n"); 10411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 10421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 10431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 10451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 10461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO: 10471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SPECTRUM: 10488503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Fast Page-Mode writes */ 10498503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQRF, 0xb0); 10501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 10511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO4: 10531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO 10548503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* ### INCOMPLETE!! */ 10558503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQRF, 0xb8); 10561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 10571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_ALPINE: 10588f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt case BT_SD64: 10591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_GD5480: 10601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_LAGUNA: 106178d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt case BT_LAGUNAB: 10621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* do nothing */ 10631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 10641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 106675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_warn(info->device, "unknown board\n"); 10671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 10681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 10691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10708503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* mode register: 256 color mode */ 10718503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, VGA_GFX_MODE, 64); 107248c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt if (cinfo->multiplexing) 10738503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* hidden dac reg: 1280x1024 */ 10748503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WHDR(cinfo, 0x4a); 10751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else 10768503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* hidden dac: nothing */ 10778503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WHDR(cinfo, 0); 10781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 10791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /****************************************************** 10811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 10821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 16 bpp 10831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 10841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 10851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else if (var->bits_per_pixel == 16) { 108775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "preparing for 16 bit deep display\n"); 10881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 10891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 1090060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt case BT_SPECTRUM: 10918503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 0x87); 10928503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Fast Page-Mode writes */ 10938503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQRF, 0xb0); 10941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 10951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 10961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO: 10978503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 0x27); 10988503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Fast Page-Mode writes */ 10998503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQRF, 0xb0); 11001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11028f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt case BT_SD64: 11031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO4: 11041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_ALPINE: 11058f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt /* Extended Sequencer Mode: 256c col. mode */ 1106df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt vga_wseq(regbase, CL_SEQR7, 1107df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt cinfo->doubleVCLK ? 0xa3 : 0xa7); 11081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_GD5480: 11118503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 0x17); 11121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* We already set SRF and SR1F */ 11131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_LAGUNA: 111678d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt case BT_LAGUNAB: 11178503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 11188503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_rseq(regbase, CL_SEQR7) & ~0x01); 11196e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt control |= 0x2000; 11206e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt format |= 0x1400; 11216e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt threshold |= 0x10; 11221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 112575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_warn(info->device, "unknown Board\n"); 11261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 11281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11298503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* mode register: 256 color mode */ 11308503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, VGA_GFX_MODE, 64); 11311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_PCI 1132df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1); 11331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#elif defined(CONFIG_ZORRO) 11341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */ 11358503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */ 11361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 11371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 11381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /****************************************************** 11401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 11417cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt * 24 bpp 11421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 11431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 11441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11457cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt else if (var->bits_per_pixel == 24) { 11467cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt dev_dbg(info->device, "preparing for 24 bit deep display\n"); 11471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 11481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 1149060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt case BT_SPECTRUM: 11508503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 0x85); 11518503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Fast Page-Mode writes */ 11528503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQRF, 0xb0); 11531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO: 11568503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 0x25); 11578503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Fast Page-Mode writes */ 11588503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQRF, 0xb0); 11591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11618f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt case BT_SD64: 11621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO4: 11631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_ALPINE: 11648f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt /* Extended Sequencer Mode: 256c col. mode */ 11657cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 0xa5); 11661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_GD5480: 11697cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 0x15); 11701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* We already set SRF and SR1F */ 11711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_LAGUNA: 117478d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt case BT_LAGUNAB: 11758503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, CL_SEQR7, 11768503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_rseq(regbase, CL_SEQR7) & ~0x01); 11777cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt control |= 0x4000; 11787cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt format |= 0x2400; 11796e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt threshold |= 0x20; 11801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 118375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_warn(info->device, "unknown Board\n"); 11841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 11851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 11861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11878503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* mode register: 256 color mode */ 11888503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, VGA_GFX_MODE, 64); 11898503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* hidden dac reg: 8-8-8 mode (24 or 32) */ 11908503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WHDR(cinfo, 0xc5); 11911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 11921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /****************************************************** 11941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 11951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * unknown/unsupported bpp 11961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 11971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 11981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 11998503df65976d0f845f49e8debff55c031635754eKrzysztof Helt else 120075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_err(info->device, 120175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt "What's this? requested color depth == %d.\n", 12021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds var->bits_per_pixel); 12031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12046683e01e2c950f635a6c0e2bbc80db1b1838311fKrzysztof Helt pitch = info->fix.line_length >> 3; 12056683e01e2c950f635a6c0e2bbc80db1b1838311fKrzysztof Helt vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff); 12061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = 0x22; 12076683e01e2c950f635a6c0e2bbc80db1b1838311fKrzysztof Helt if (pitch & 0x100) 12081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x10; /* offset overflow bit */ 12091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12108503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* screen start addr #16-18, fastpagemode cycles */ 12118503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(regbase, CL_CRT1B, tmp); 12121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1213213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt /* screen start address bit 19 */ 1214213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) 12156683e01e2c950f635a6c0e2bbc80db1b1838311fKrzysztof Helt vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1); 12168503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 121778d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (is_laguna(cinfo)) { 1218213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt tmp = 0; 1219213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt if ((htotal + 5) & 256) 1220213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt tmp |= 128; 1221213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt if (hdispend & 256) 1222213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt tmp |= 64; 1223213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt if (hsyncstart & 256) 1224213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt tmp |= 48; 1225213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt if (vtotal & 1024) 1226213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt tmp |= 8; 1227213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt if (vdispend & 1024) 1228213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt tmp |= 4; 1229213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt if (vsyncstart & 1024) 1230213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt tmp |= 3; 1231213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt 1232213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt vga_wcrt(regbase, CL_CRT1E, tmp); 1233213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt dev_dbg(info->device, "CRT1e: %d\n", tmp); 1234213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt } 1235213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt 12368503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* pixel panning */ 12378503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(regbase, CL_AR33, 0); 12381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* [ EGS: SetOffset(); ] */ 12401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */ 12418503df65976d0f845f49e8debff55c031635754eKrzysztof Helt AttrOn(cinfo); 12428503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 124378d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (is_laguna(cinfo)) { 12446e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt /* no tiles */ 12456e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402); 12466e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt fb_writew(format, cinfo->laguna_mmio + 0xc0); 12476e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt fb_writew(threshold, cinfo->laguna_mmio + 0xea); 12486e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt } 12491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* finally, turn on everything - turn off "FullBandwidth" bit */ 12501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* also, set "DotClock%2" bit where requested */ 12511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = 0x01; 12521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ? 12541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->vmode & FB_VMODE_CLOCK_HALVE) 12551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x08; 12561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds*/ 12571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12588503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp); 125975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "CL_SEQR1: %d\n", tmp); 12601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CIRRUSFB_DEBUG 126275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt cirrusfb_dbg_reg_dump(info, NULL); 12631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 12641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 12661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 12671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* for some reason incomprehensible to me, cirrusfb requires that you write 12691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * the registers twice for the settings to take..grr. -dte */ 12708503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int cirrusfb_set_par(struct fb_info *info) 12711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 12728503df65976d0f845f49e8debff55c031635754eKrzysztof Helt cirrusfb_set_par_foo(info); 12738503df65976d0f845f49e8debff55c031635754eKrzysztof Helt return cirrusfb_set_par_foo(info); 12741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 12751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12768503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green, 12778503df65976d0f845f49e8debff55c031635754eKrzysztof Helt unsigned blue, unsigned transp, 12788503df65976d0f845f49e8debff55c031635754eKrzysztof Helt struct fb_info *info) 12791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 12801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct cirrusfb_info *cinfo = info->par; 12811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (regno > 255) 12831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return -EINVAL; 12841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (info->fix.visual == FB_VISUAL_TRUECOLOR) { 12861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 v; 12871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds red >>= (16 - info->var.red.length); 12881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds green >>= (16 - info->var.green.length); 12891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds blue >>= (16 - info->var.blue.length); 12901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 12918503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (regno >= 16) 12921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 1; 12931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds v = (red << info->var.red.offset) | 12941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (green << info->var.green.offset) | 12951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (blue << info->var.blue.offset); 12961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1297060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt cinfo->pseudo_palette[regno] = v; 12981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 12991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 13001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13018503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (info->var.bits_per_pixel == 8) 13028503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10); 13031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 13051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 13071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/************************************************************************* 13091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cirrusfb_pan_display() 13101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds performs display panning - provided hardware permits this 13121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds**************************************************************************/ 13138503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int cirrusfb_pan_display(struct fb_var_screeninfo *var, 13148503df65976d0f845f49e8debff55c031635754eKrzysztof Helt struct fb_info *info) 13151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 131699a4584752bb41330342a427d014482525de7433Krzysztof Helt int xoffset; 13171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long base; 1318213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt unsigned char tmp, xpix; 13191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct cirrusfb_info *cinfo = info->par; 13201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* no range checks for xoffset and yoffset, */ 13221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* as fb_pan_display has already done this */ 13231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->vmode & FB_VMODE_YWRAP) 13241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return -EINVAL; 13251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds xoffset = var->xoffset * info->var.bits_per_pixel / 8; 13271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 132899a4584752bb41330342a427d014482525de7433Krzysztof Helt base = var->yoffset * info->fix.line_length + xoffset; 13291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (info->var.bits_per_pixel == 1) { 13311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* base is already correct */ 13321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds xpix = (unsigned char) (var->xoffset % 8); 13331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 13341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds base /= 4; 13351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds xpix = (unsigned char) ((xoffset % 4) * 2); 13361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 13371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 133878d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (!is_laguna(cinfo)) 13391b48cb563d59e03dbf530174f30c0ed3b6fba513Krzysztof Helt cirrusfb_WaitBLT(cinfo->regbase); 13401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* lower 8 + 8 bits of screen start address */ 134299a4584752bb41330342a427d014482525de7433Krzysztof Helt vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff); 134399a4584752bb41330342a427d014482525de7433Krzysztof Helt vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff); 13441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1345213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt /* 0xf2 is %11110010, exclude tmp bits */ 1346213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2; 13471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* construct bits 16, 17 and 18 of screen start address */ 13481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (base & 0x10000) 13491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x01; 13501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (base & 0x20000) 13511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x04; 13521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (base & 0x40000) 13531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= 0x08; 13541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1355213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt vga_wcrt(cinfo->regbase, CL_CRT1B, tmp); 13561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* construct bit 19 of screen start address */ 135848c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) { 135978d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt tmp = vga_rcrt(cinfo->regbase, CL_CRT1D); 136078d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (is_laguna(cinfo)) 136178d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt tmp = (tmp & ~0x18) | ((base >> 16) & 0x18); 136278d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt else 136378d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt tmp = (tmp & ~0x80) | ((base >> 12) & 0x80); 136448c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt vga_wcrt(cinfo->regbase, CL_CRT1D, tmp); 136548c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt } 13661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13678503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* write pixel panning value to AR33; this does not quite work in 8bpp 13688503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * 13698503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * ### Piccolo..? Will this work? 13708503df65976d0f845f49e8debff55c031635754eKrzysztof Helt */ 13711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (info->var.bits_per_pixel == 1) 13728503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, CL_AR33, xpix); 13731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13748503df65976d0f845f49e8debff55c031635754eKrzysztof Helt return 0; 13751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 13761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13778503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int cirrusfb_blank(int blank_mode, struct fb_info *info) 13781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 13791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 13808503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * Blank the screen if blank_mode != 0, else unblank. If blank == NULL 13818503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * then the caller blanks by setting the CLUT (Color Look Up Table) 13828503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking 13838503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * failed due to e.g. a video mode which doesn't support it. 13848503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * Implements VESA suspend and powerdown modes on hardware that 13858503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * supports disabling hsync/vsync: 13868503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * blank_mode == 2: suspend vsync 13878503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * blank_mode == 3: suspend hsync 13888503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * blank_mode == 4: powerdown 13891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 13901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char val; 13911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct cirrusfb_info *cinfo = info->par; 13921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int current_mode = cinfo->blank_mode; 13931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 139475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode); 13951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 13961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (info->state != FBINFO_STATE_RUNNING || 13971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds current_mode == blank_mode) { 139875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "EXIT, returning 0\n"); 13991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 14001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 14011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Undo current */ 14031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (current_mode == FB_BLANK_NORMAL || 1404213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt current_mode == FB_BLANK_UNBLANK) 14058503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* clear "FullBandwidth" bit */ 1406213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt val = 0; 1407213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt else 14088503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* set "FullBandwidth" bit */ 1409213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt val = 0x20; 1410213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt 1411213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf; 1412213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val); 14131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (blank_mode) { 14151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case FB_BLANK_UNBLANK: 14161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case FB_BLANK_NORMAL: 1417213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt val = 0x00; 14181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case FB_BLANK_VSYNC_SUSPEND: 1420213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt val = 0x04; 14211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case FB_BLANK_HSYNC_SUSPEND: 1423213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt val = 0x02; 14241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case FB_BLANK_POWERDOWN: 1426213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt val = 0x06; 14271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 142975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "EXIT, returning 1\n"); 14301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 1; 14311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 14321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1433213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt vga_wgfx(cinfo->regbase, CL_GRE, val); 1434213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt 14351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cinfo->blank_mode = blank_mode; 143675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "EXIT, returning 0\n"); 14371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Let fbcon do a soft blank for us */ 14391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0; 14401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1441213d4bdd8cd405d9ba59ee78165b8c870f83a018Krzysztof Helt 14421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/**** END Hardware specific Routines **************************************/ 14431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/****************************************************************************/ 14441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/**** BEGIN Internal Routines ***********************************************/ 14451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14469199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Heltstatic void init_vgachip(struct fb_info *info) 14471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 14489199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt struct cirrusfb_info *cinfo = info->par; 14491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds const struct cirrusfb_board_info_rec *bi; 14501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14518503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(cinfo != NULL); 14521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds bi = &cirrusfb_board_info[cinfo->btype]; 14541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* reset board globally */ 14561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 14571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 14588503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, 0x01); 14598503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(500); 14608503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, 0x51); 14618503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(500); 14621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO: 14648503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR2(cinfo, 0xff); 14658503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(500); 14661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SD64: 14681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SPECTRUM: 14698503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, 0x1f); 14708503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(500); 14718503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, 0x4f); 14728503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(500); 14731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICASSO4: 14758503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* disable flickerfixer */ 14768503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(cinfo->regbase, CL_CRT51, 0x00); 14778503df65976d0f845f49e8debff55c031635754eKrzysztof Helt mdelay(100); 14788503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* mode */ 14798503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GR31, 0x00); 14807cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt case BT_GD5480: /* fall through */ 14818503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* from Klaus' NetBSD driver: */ 14828503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GR2F, 0x00); 14837cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt case BT_ALPINE: /* fall through */ 14847cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt /* put blitter into 542x compat */ 14857cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GR33, 0x00); 14861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14881b48cb563d59e03dbf530174f30c0ed3b6fba513Krzysztof Helt case BT_LAGUNA: 148978d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt case BT_LAGUNAB: 14901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Nothing to do to reset the board. */ 14911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 149475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_err(info->device, "Warning: Unknown board type\n"); 14951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 14961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 14971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 14989199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt /* make sure RAM size set by this point */ 14999199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt assert(info->screen_size > 0); 15001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* the P4 is not fully initialized here; I rely on it having been */ 15021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* inited under AmigaOS already, which seems to work just fine */ 15038503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* (Klaus advised to do it this way) */ 15041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype != BT_PICASSO4) { 15068503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */ 15078503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, CL_POS102, 0x01); 15088503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */ 15091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype != BT_SD64) 15118503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, CL_VSSM2, 0x01); 15121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15138503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* reset sequencer logic */ 15141b48cb563d59e03dbf530174f30c0ed3b6fba513Krzysztof Helt vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03); 15151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15168503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* FullBandwidth (video off) and 8/9 dot clock */ 15178503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); 15181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15198503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* "magic cookie" - doesn't make any sense to me.. */ 15208503df65976d0f845f49e8debff55c031635754eKrzysztof Helt/* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */ 15218503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* unlock all extension registers */ 15228503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR6, 0x12); 15231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 15251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_GD5480: 15268503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQRF, 0x98); 15271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 15281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_ALPINE: 15291b48cb563d59e03dbf530174f30c0ed3b6fba513Krzysztof Helt case BT_LAGUNA: 153078d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt case BT_LAGUNAB: 15311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 15321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SD64: 1533df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt#ifdef CONFIG_ZORRO 15348503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8); 1535df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt#endif 15361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 15371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 15388503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f); 15398503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0); 15401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 15411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 15421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 15438503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* plane mask: nothing */ 15448503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); 15458503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* character map select: doesn't even matter in gx mode */ 15468503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); 154748c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt /* memory mode: chain4, ext. memory */ 154848c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a); 15491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* controller-internal base address of video memory */ 15511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (bi->init_sr07) 15528503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07); 15531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15548503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */ 15558503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* EEPROM control: shouldn't be necessary to write to this at all.. */ 15561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15578503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* graphics cursor X position (incomplete; position gives rem. 3 bits */ 15588503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR10, 0x00); 15598503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* graphics cursor Y position (..."... ) */ 15608503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR11, 0x00); 15618503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* graphics cursor attributes */ 15628503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR12, 0x00); 15638503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* graphics cursor pattern address */ 15648503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR13, 0x00); 15651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* writing these on a P4 might give problems.. */ 15671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype != BT_PICASSO4) { 15688503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* configuration readback and ext. color */ 15698503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR17, 0x00); 15708503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* signature generator */ 15718503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR18, 0x02); 15721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 15731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 15748503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Screen A preset row scan: none */ 15758503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); 15768503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Text cursor start: disable text cursor */ 15778503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); 15788503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Text cursor end: - */ 15798503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); 15808503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* text cursor location high: 0 */ 15818503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); 15828503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* text cursor location low: 0 */ 15838503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); 15848503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 15858503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Underline Row scanline: - */ 15868503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); 15871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* ### add 0x40 for text modes with > 30 MHz pixclock */ 15888503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* ext. display controls: ext.adr. wrap */ 15898503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02); 15908503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 1591ff0c26424c1d993d8d1e04f72f1d428e935798daMasanari Iida /* Set/Reset registers: - */ 15928503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); 15938503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Set/Reset enable: - */ 15948503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); 15958503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Color Compare: - */ 15968503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); 15978503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Data Rotate: - */ 15988503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); 15998503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Read Map Select: - */ 16008503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); 16018503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */ 16028503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00); 16038503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Miscellaneous: memory map base address, graphics mode */ 16048503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01); 16058503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Color Don't care: involve all planes */ 16068503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); 16078503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Bit Mask: no mask at all */ 16088503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); 16091b48cb563d59e03dbf530174f30c0ed3b6fba513Krzysztof Helt 1610df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 || 1611df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt is_laguna(cinfo)) 16128503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* (5434 can't have bit 3 set for bitblt) */ 16138503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GRB, 0x20); 16141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds else 16158503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Graphics controller mode extensions: finer granularity, 16168503df65976d0f845f49e8debff55c031635754eKrzysztof Helt * 8byte data latches 16178503df65976d0f845f49e8debff55c031635754eKrzysztof Helt */ 16188503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GRB, 0x28); 16198503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 16208503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */ 16218503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */ 16228503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */ 16238503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Background color byte 1: - */ 16248503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */ 16258503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */ 16268503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 16278503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Attribute Controller palette registers: "identity mapping" */ 16288503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00); 16298503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01); 16308503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02); 16318503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03); 16328503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04); 16338503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05); 16348503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06); 16358503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07); 16368503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08); 16378503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09); 16388503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a); 16398503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b); 16408503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c); 16418503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d); 16428503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e); 16438503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f); 16448503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 16458503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Attribute Controller mode: graphics mode */ 16468503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01); 16478503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Overscan color reg.: reg. 0 */ 16488503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); 16498503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Color Plane enable: Enable all 4 planes */ 16508503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); 16518503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* Color Select: - */ 16528503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); 16538503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 16548503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */ 16551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 16568503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT Start/status: Blitter reset */ 16578503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GR31, 0x04); 16588503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* - " - : "end-of-reset" */ 16598503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(cinfo->regbase, CL_GR31, 0x00); 16601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 16611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* misc... */ 16628503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WHDR(cinfo, 0); /* Hidden DAC register: - */ 16631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 16641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 16651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 16668503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void switch_monitor(struct cirrusfb_info *cinfo, int on) 16671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 16681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO /* only works on Zorro boards */ 16691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds static int IsOn = 0; /* XXX not ok for multiple boards */ 16701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 16711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO4) 16721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; /* nothing to switch */ 16731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_ALPINE) 16741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; /* nothing to switch */ 16751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_GD5480) 16761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; /* nothing to switch */ 16771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO) { 16781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if ((on && !IsOn) || (!on && IsOn)) 16798503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, 0xff); 16801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 16811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 16821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (on) { 16831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 16841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SD64: 16858503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, cinfo->SFR | 0x21); 16861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 16871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 16888503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, cinfo->SFR | 0x28); 16891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 16901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SPECTRUM: 16918503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, 0x6f); 16921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 16931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: /* do nothing */ break; 16941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 16951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 16961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (cinfo->btype) { 16971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SD64: 16988503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, cinfo->SFR & 0xde); 16991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 17001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_PICCOLO: 17018503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, cinfo->SFR & 0xd7); 17021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 17031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case BT_SPECTRUM: 17048503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WSFR(cinfo, 0x4f); 17051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 170675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt default: /* do nothing */ 170775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt break; 17081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 17091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 17101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CONFIG_ZORRO */ 17111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 17121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/******************************************/ 17141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Linux 2.6-style accelerated functions */ 17151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/******************************************/ 17161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17178343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Heltstatic int cirrusfb_sync(struct fb_info *info) 17188343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt{ 17198343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt struct cirrusfb_info *cinfo = info->par; 17208343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt 17218343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt if (!is_laguna(cinfo)) { 17228343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03) 17238343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt cpu_relax(); 17248343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt } 17258343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt return 0; 17268343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt} 17278343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt 17288503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void cirrusfb_fillrect(struct fb_info *info, 17298503df65976d0f845f49e8debff55c031635754eKrzysztof Helt const struct fb_fillrect *region) 17301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 17311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_fillrect modded; 17321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int vxres, vyres; 1733060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt struct cirrusfb_info *cinfo = info->par; 1734060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt int m = info->var.bits_per_pixel; 1735060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? 1736060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt cinfo->pseudo_palette[region->color] : region->color; 17371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (info->state != FBINFO_STATE_RUNNING) 17391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 17401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (info->flags & FBINFO_HWACCEL_DISABLED) { 17411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cfb_fillrect(info, region); 17421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 17431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 17441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds vxres = info->var.xres_virtual; 17461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds vyres = info->var.yres_virtual; 17471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds memcpy(&modded, region, sizeof(struct fb_fillrect)); 17491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17508503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (!modded.width || !modded.height || 17511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds modded.dx >= vxres || modded.dy >= vyres) 17521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 17531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17548503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (modded.dx + modded.width > vxres) 17558503df65976d0f845f49e8debff55c031635754eKrzysztof Helt modded.width = vxres - modded.dx; 17568503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (modded.dy + modded.height > vyres) 17578503df65976d0f845f49e8debff55c031635754eKrzysztof Helt modded.height = vyres - modded.dy; 17581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1759060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt cirrusfb_RectFill(cinfo->regbase, 1760060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt info->var.bits_per_pixel, 1761060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt (region->dx * m) / 8, region->dy, 1762060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt (region->width * m) / 8, region->height, 17639e848062533207130667f6eaa748549367ccbedfKrzysztof Helt color, color, 17649e848062533207130667f6eaa748549367ccbedfKrzysztof Helt info->fix.line_length, 0x40); 17651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 17661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17678503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void cirrusfb_copyarea(struct fb_info *info, 17688503df65976d0f845f49e8debff55c031635754eKrzysztof Helt const struct fb_copyarea *area) 17691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 17701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_copyarea modded; 17711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 vxres, vyres; 1772060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt struct cirrusfb_info *cinfo = info->par; 1773060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt int m = info->var.bits_per_pixel; 17741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (info->state != FBINFO_STATE_RUNNING) 17761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 17771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (info->flags & FBINFO_HWACCEL_DISABLED) { 17781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cfb_copyarea(info, area); 17791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 17801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 17811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds vxres = info->var.xres_virtual; 17831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds vyres = info->var.yres_virtual; 1784060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt memcpy(&modded, area, sizeof(struct fb_copyarea)); 17851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17868503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (!modded.width || !modded.height || 17871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds modded.sx >= vxres || modded.sy >= vyres || 17881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds modded.dx >= vxres || modded.dy >= vyres) 17891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return; 17901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 17918503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (modded.sx + modded.width > vxres) 17928503df65976d0f845f49e8debff55c031635754eKrzysztof Helt modded.width = vxres - modded.sx; 17938503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (modded.dx + modded.width > vxres) 17948503df65976d0f845f49e8debff55c031635754eKrzysztof Helt modded.width = vxres - modded.dx; 17958503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (modded.sy + modded.height > vyres) 17968503df65976d0f845f49e8debff55c031635754eKrzysztof Helt modded.height = vyres - modded.sy; 17978503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (modded.dy + modded.height > vyres) 17988503df65976d0f845f49e8debff55c031635754eKrzysztof Helt modded.height = vyres - modded.dy; 17991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1800060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel, 1801060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt (area->sx * m) / 8, area->sy, 1802060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt (area->dx * m) / 8, area->dy, 1803060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt (area->width * m) / 8, area->height, 18040ff1edeef222ebed71499135a8cc259b107d85fdKrzysztof Helt info->fix.line_length); 1805060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt 18061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 18071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 18088503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void cirrusfb_imageblit(struct fb_info *info, 18098503df65976d0f845f49e8debff55c031635754eKrzysztof Helt const struct fb_image *image) 18101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 18111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct cirrusfb_info *cinfo = info->par; 18127cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4; 18131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 18149e848062533207130667f6eaa748549367ccbedfKrzysztof Helt if (info->state != FBINFO_STATE_RUNNING) 18159e848062533207130667f6eaa748549367ccbedfKrzysztof Helt return; 1816df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt /* Alpine/SD64 does not work at 24bpp ??? */ 1817df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) 1818df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt cfb_imageblit(info, image); 1819df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) && 1820df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt op == 0xc) 18219e848062533207130667f6eaa748549367ccbedfKrzysztof Helt cfb_imageblit(info, image); 18229e848062533207130667f6eaa748549367ccbedfKrzysztof Helt else { 18239e848062533207130667f6eaa748549367ccbedfKrzysztof Helt unsigned size = ((image->width + 7) >> 3) * image->height; 18249e848062533207130667f6eaa748549367ccbedfKrzysztof Helt int m = info->var.bits_per_pixel; 18259e848062533207130667f6eaa748549367ccbedfKrzysztof Helt u32 fg, bg; 18269e848062533207130667f6eaa748549367ccbedfKrzysztof Helt 18279e848062533207130667f6eaa748549367ccbedfKrzysztof Helt if (info->var.bits_per_pixel == 8) { 18289e848062533207130667f6eaa748549367ccbedfKrzysztof Helt fg = image->fg_color; 18299e848062533207130667f6eaa748549367ccbedfKrzysztof Helt bg = image->bg_color; 18309e848062533207130667f6eaa748549367ccbedfKrzysztof Helt } else { 18319e848062533207130667f6eaa748549367ccbedfKrzysztof Helt fg = ((u32 *)(info->pseudo_palette))[image->fg_color]; 18329e848062533207130667f6eaa748549367ccbedfKrzysztof Helt bg = ((u32 *)(info->pseudo_palette))[image->bg_color]; 18339e848062533207130667f6eaa748549367ccbedfKrzysztof Helt } 18347cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt if (info->var.bits_per_pixel == 24) { 18357cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt /* clear background first */ 18367cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt cirrusfb_RectFill(cinfo->regbase, 18377cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt info->var.bits_per_pixel, 18387cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt (image->dx * m) / 8, image->dy, 18397cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt (image->width * m) / 8, 18407cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt image->height, 18417cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt bg, bg, 18427cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt info->fix.line_length, 0x40); 18437cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt } 18449e848062533207130667f6eaa748549367ccbedfKrzysztof Helt cirrusfb_RectFill(cinfo->regbase, 18459e848062533207130667f6eaa748549367ccbedfKrzysztof Helt info->var.bits_per_pixel, 18469e848062533207130667f6eaa748549367ccbedfKrzysztof Helt (image->dx * m) / 8, image->dy, 18479e848062533207130667f6eaa748549367ccbedfKrzysztof Helt (image->width * m) / 8, image->height, 18489e848062533207130667f6eaa748549367ccbedfKrzysztof Helt fg, bg, 18497cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt info->fix.line_length, op); 18509e848062533207130667f6eaa748549367ccbedfKrzysztof Helt memcpy(info->screen_base, image->data, size); 18519e848062533207130667f6eaa748549367ccbedfKrzysztof Helt } 18521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 18531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 18541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_PCI 18558503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic int release_io_ports; 18561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 18571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Pulled the logic from XFree86 Cirrus driver to get the memory size, 18581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * based on the DRAM bandwidth bit and DRAM bank switching bit. This 18591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * works with 1MB, 2MB and 4MB configurations (which the Motorola boards 18601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * seem to have. */ 186148c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic unsigned int cirrusfb_get_memsize(struct fb_info *info, 186248c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartman u8 __iomem *regbase) 18631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 18641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long mem; 186555a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt struct cirrusfb_info *cinfo = info->par; 18661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 186778d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (is_laguna(cinfo)) { 186855a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt unsigned char SR14 = vga_rseq(regbase, CL_SEQR14); 186955a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt 187055a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt mem = ((SR14 & 7) + 1) << 20; 187155a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt } else { 187255a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt unsigned char SRF = vga_rseq(regbase, CL_SEQRF); 187355a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt switch ((SRF & 0x18)) { 187455a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt case 0x08: 187555a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt mem = 512 * 1024; 187655a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt break; 187755a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt case 0x10: 187855a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt mem = 1024 * 1024; 187955a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt break; 188055a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt /* 64-bit DRAM data bus width; assume 2MB. 188155a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt * Also indicates 2MB memory on the 5430. 188255a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt */ 188355a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt case 0x18: 188455a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt mem = 2048 * 1024; 188555a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt break; 188655a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt default: 188755a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt dev_warn(info->device, "Unknown memory size!\n"); 188855a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt mem = 1024 * 1024; 188955a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt } 189055a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt /* If DRAM bank switching is enabled, there must be 189155a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt * twice as much memory installed. (4MB on the 5434) 189255a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt */ 1893df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0) 189455a4ea6ab0fff0c02f101a60d2ba4f1794990499Krzysztof Helt mem *= 2; 18951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 18968503df65976d0f845f49e8debff55c031635754eKrzysztof Helt 18971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */ 18981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return mem; 18991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 19001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19018503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void get_pci_addrs(const struct pci_dev *pdev, 19028503df65976d0f845f49e8debff55c031635754eKrzysztof Helt unsigned long *display, unsigned long *registers) 19031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 19048503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(pdev != NULL); 19058503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(display != NULL); 19068503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(registers != NULL); 19071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *display = 0; 19091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *registers = 0; 19101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* This is a best-guess for now */ 19121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) { 19141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *display = pci_resource_start(pdev, 1); 19151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *registers = pci_resource_start(pdev, 0); 19161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 19171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *display = pci_resource_start(pdev, 0); 19181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *registers = pci_resource_start(pdev, 1); 19191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 19201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19218503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(*display != 0); 19221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 19231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19249199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Heltstatic void cirrusfb_pci_unmap(struct fb_info *info) 19251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 192664beab14f53790e59a4e0a9ef1d752c12ad54a62Krzysztof Helt struct pci_dev *pdev = to_pci_dev(info->device); 19276e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt struct cirrusfb_info *cinfo = info->par; 19281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19296e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt if (cinfo->laguna_mmio == NULL) 19306e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt iounmap(cinfo->laguna_mmio); 19319199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt iounmap(info->screen_base); 19321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if 0 /* if system didn't claim this region, we would... */ 19331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds release_mem_region(0xA0000, 65535); 19341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 19351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (release_io_ports) 19361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds release_region(0x3C0, 32); 19371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_release_regions(pdev); 19381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 19391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CONFIG_PCI */ 19401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO 1942f5ee051e748ae007b972c7e1b6a0588b8ac9ba40Al Virostatic void cirrusfb_zorro_unmap(struct fb_info *info) 19431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1944d91f5bb69adde86173071cf7fffbdf705ae8c6e7Al Viro struct cirrusfb_info *cinfo = info->par; 194564beab14f53790e59a4e0a9ef1d752c12ad54a62Krzysztof Helt struct zorro_dev *zdev = to_zorro_dev(info->device); 194664beab14f53790e59a4e0a9ef1d752c12ad54a62Krzysztof Helt 19470e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (info->fix.smem_start > 16 * MB_) 19489199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt iounmap(info->screen_base); 19490e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (info->fix.mmio_start > 16 * MB_) 19500e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven iounmap(cinfo->regbase); 19510e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 19520e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven zorro_release_device(zdev); 19531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 19541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CONFIG_ZORRO */ 19551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 195648c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt/* function table of the above functions */ 195748c329e906f834711906ab4b0986ea0e857aff16Krzysztof Heltstatic struct fb_ops cirrusfb_ops = { 195848c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .owner = THIS_MODULE, 195948c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_open = cirrusfb_open, 196048c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_release = cirrusfb_release, 196148c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_setcolreg = cirrusfb_setcolreg, 196248c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_check_var = cirrusfb_check_var, 196348c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_set_par = cirrusfb_set_par, 196448c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_pan_display = cirrusfb_pan_display, 196548c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_blank = cirrusfb_blank, 196648c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_fillrect = cirrusfb_fillrect, 196748c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_copyarea = cirrusfb_copyarea, 19688343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt .fb_sync = cirrusfb_sync, 196948c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt .fb_imageblit = cirrusfb_imageblit, 197048c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt}; 197148c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt 197248c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic int cirrusfb_set_fbinfo(struct fb_info *info) 19731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 19749199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt struct cirrusfb_info *cinfo = info->par; 19751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_var_screeninfo *var = &info->var; 19761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->pseudo_palette = cinfo->pseudo_palette; 19781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->flags = FBINFO_DEFAULT 19791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | FBINFO_HWACCEL_XPAN 19801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | FBINFO_HWACCEL_YPAN 19811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | FBINFO_HWACCEL_FILLRECT 19829e848062533207130667f6eaa748549367ccbedfKrzysztof Helt | FBINFO_HWACCEL_IMAGEBLIT 19831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds | FBINFO_HWACCEL_COPYAREA; 1984614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt if (noaccel || is_laguna(cinfo)) { 19851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->flags |= FBINFO_HWACCEL_DISABLED; 1986614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt info->fix.accel = FB_ACCEL_NONE; 1987614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt } else 1988614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt info->fix.accel = FB_ACCEL_CIRRUS_ALPINE; 1989614c0dc93284404be2a4d5750c79bb95f2b6c980Krzysztof Helt 19901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->fbops = &cirrusfb_ops; 19919e848062533207130667f6eaa748549367ccbedfKrzysztof Helt 19921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_GD5480) { 19931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (var->bits_per_pixel == 16) 19941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->screen_base += 1 * MB_; 19951cea9a9a6c3c718eea42f6a936d1e98136d3d011Krzysztof Helt if (var->bits_per_pixel == 32) 19961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->screen_base += 2 * MB_; 19971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 19981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 19991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Fill fix common fields */ 20001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name, 20011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds sizeof(info->fix.id)); 20021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* monochrome: only 1 memory plane */ 20041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 8 bit and above: Use whole memory area */ 20059199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt info->fix.smem_len = info->screen_size; 20069199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt if (var->bits_per_pixel == 1) 20079199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt info->fix.smem_len /= 4; 20081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->fix.type_aux = 0; 20091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->fix.xpanstep = 1; 20101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->fix.ypanstep = 1; 20111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->fix.ywrapstep = 0; 20121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* FIXME: map region at 0xB8000 if available, fill in here */ 20141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->fix.mmio_len = 0; 20151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds fb_alloc_cmap(&info->cmap, 256, 0); 20171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 20191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 20201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 202148c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic int cirrusfb_register(struct fb_info *info) 20221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 20239199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt struct cirrusfb_info *cinfo = info->par; 20241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int err; 20251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* sanity checks */ 202748c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt assert(cinfo->btype != BT_NONE); 20281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2029a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt /* set all the vital stuff */ 2030a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt cirrusfb_set_fbinfo(info); 2031a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt 203275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base); 20331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2034a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); 2035a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt if (!err) { 203675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "wrong initial video mode\n"); 2037a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt err = -EINVAL; 2038a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt goto err_dealloc_cmap; 2039a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt } 2040a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt 20411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info->var.activate = FB_ACTIVATE_NOW; 20421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 204399a4584752bb41330342a427d014482525de7433Krzysztof Helt err = cirrusfb_check_var(&info->var, info); 20441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (err < 0) { 20451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* should never happen */ 204675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, 204775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt "choking on default var... umm, no good.\n"); 2048a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt goto err_dealloc_cmap; 20491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 20501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds err = register_framebuffer(info); 20521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (err < 0) { 205375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_err(info->device, 205475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt "could not register fb device; err = %d!\n", err); 20551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds goto err_dealloc_cmap; 20561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 20571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 20591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldserr_dealloc_cmap: 20611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds fb_dealloc_cmap(&info->cmap); 20621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return err; 20631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 20641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 206548c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic void cirrusfb_cleanup(struct fb_info *info) 20661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 20671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct cirrusfb_info *cinfo = info->par; 20681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20698503df65976d0f845f49e8debff55c031635754eKrzysztof Helt switch_monitor(cinfo, 0); 20708503df65976d0f845f49e8debff55c031635754eKrzysztof Helt unregister_framebuffer(info); 20718503df65976d0f845f49e8debff55c031635754eKrzysztof Helt fb_dealloc_cmap(&info->cmap); 207275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "Framebuffer unregistered\n"); 20739199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt cinfo->unmap(info); 2074060b6002b1413f4ab76c9f41bf479ccea4153092Krzysztof Helt framebuffer_release(info); 20751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 20761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_PCI 207848c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic int cirrusfb_pci_register(struct pci_dev *pdev, 207948c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartman const struct pci_device_id *ent) 20801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 20811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct cirrusfb_info *cinfo; 20821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_info *info; 20831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long board_addr, board_size; 20841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int ret; 20851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ret = pci_enable_device(pdev); 20871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (ret < 0) { 20881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n"); 20891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds goto err_out; 20901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 20911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev); 20931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!info) { 20941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds printk(KERN_ERR "cirrusfb: could not allocate memory\n"); 20951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ret = -ENOMEM; 209678d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt goto err_out; 20971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 20981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 20991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cinfo = info->par; 210048c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt cinfo->btype = (enum cirrus_board) ent->driver_data; 21011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 210275ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, 210375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n", 210448c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt (unsigned long long)pdev->resource[0].start, cinfo->btype); 210575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, " base address 1 is 0x%Lx\n", 210675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt (unsigned long long)pdev->resource[1].start); 21071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2108933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle dev_dbg(info->device, 2109933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle "Attempt to get PCI info for Cirrus Graphics Card\n"); 2110933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start); 2111933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle /* FIXME: this forces VGA. alternatives? */ 2112933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle cinfo->regbase = NULL; 2113933ee7119fb14156f46dc8bce8218f62db13c568Paul Bolle cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000); 21141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 211575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n", 21169199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt board_addr, info->fix.mmio_start); 21171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 211848c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt board_size = (cinfo->btype == BT_GD5480) ? 211975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase); 21201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ret = pci_request_regions(pdev, "cirrusfb"); 21228503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (ret < 0) { 212375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_err(info->device, "cannot reserve region 0x%lx, abort\n", 212475ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt board_addr); 21251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds goto err_release_fb; 21261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 21271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if 0 /* if the system didn't claim this region, we would... */ 21281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!request_mem_region(0xA0000, 65535, "cirrusfb")) { 212975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_err(info->device, "cannot reserve region 0x%lx, abort\n", 213075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt 0xA0000L); 21311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ret = -EBUSY; 21321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds goto err_release_regions; 21331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 21341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 21351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (request_region(0x3C0, 32, "cirrusfb")) 21361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds release_io_ports = 1; 21371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21389199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt info->screen_base = ioremap(board_addr, board_size); 21399199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt if (!info->screen_base) { 21401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ret = -EIO; 21411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds goto err_release_legacy; 21421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 21431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21449199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt info->fix.smem_start = board_addr; 21459199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt info->screen_size = board_size; 21461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cinfo->unmap = cirrusfb_pci_unmap; 21471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 214875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_info(info->device, 214975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n", 215075ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt info->screen_size >> 10, board_addr); 21511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_set_drvdata(pdev, info); 21521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21539199ec5c5fe0cb6b03390fea2338435999e0df5cKrzysztof Helt ret = cirrusfb_register(info); 215478d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (!ret) 215578d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt return 0; 21561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 215778d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt iounmap(info->screen_base); 21581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldserr_release_legacy: 21591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (release_io_ports) 21601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds release_region(0x3C0, 32); 21611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if 0 21621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds release_mem_region(0xA0000, 65535); 21631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldserr_release_regions: 21641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 21651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_release_regions(pdev); 21661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldserr_release_fb: 216778d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (cinfo->laguna_mmio != NULL) 21686e30fc086d000d15abfe5550cc8b286335f7e132Krzysztof Helt iounmap(cinfo->laguna_mmio); 21691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds framebuffer_release(info); 21701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldserr_out: 21711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return ret; 21721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 21731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 217448c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic void cirrusfb_pci_unregister(struct pci_dev *pdev) 21751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 21761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_info *info = pci_get_drvdata(pdev); 21771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21788503df65976d0f845f49e8debff55c031635754eKrzysztof Helt cirrusfb_cleanup(info); 21791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 21801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic struct pci_driver cirrusfb_pci_driver = { 21821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "cirrusfb", 21831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .id_table = cirrusfb_pci_table, 21841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .probe = cirrusfb_pci_register, 218548c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartman .remove = cirrusfb_pci_unregister, 21861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_PM 21871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if 0 21881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .suspend = cirrusfb_pci_suspend, 21891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .resume = cirrusfb_pci_resume, 21901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 21911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 21921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 21931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CONFIG_PCI */ 21941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 21951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO 219648c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanstatic int cirrusfb_zorro_register(struct zorro_dev *z, 219748c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartman const struct zorro_device_id *ent) 21981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 21991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_info *info; 22000e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven int error; 22010e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven const struct zorrocl *zcl; 22027345de32df7ef0ab49eaa88cad1297d8572a6757Krzysztof Helt enum cirrus_board btype; 22030e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven unsigned long regbase, ramsize, rambase; 22040e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven struct cirrusfb_info *cinfo; 22051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 22061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev); 22071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!info) { 22088503df65976d0f845f49e8debff55c031635754eKrzysztof Helt printk(KERN_ERR "cirrusfb: could not allocate memory\n"); 22090e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven return -ENOMEM; 22101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 22111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 22120e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven zcl = (const struct zorrocl *)ent->driver_data; 22130e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven btype = zcl->type; 22140e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven regbase = zorro_resource_start(z) + zcl->regoffset; 22150e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven ramsize = zcl->ramsize; 22160e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (ramsize) { 22170e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven rambase = zorro_resource_start(z) + zcl->ramoffset; 2218e78bb882bf318bb41e17b33729cca3bdd26b42a0Geert Uytterhoeven if (zorro_resource_len(z) == 64 * MB_) { 2219e78bb882bf318bb41e17b33729cca3bdd26b42a0Geert Uytterhoeven /* Quirk for 64 MiB Picasso IV */ 2220e78bb882bf318bb41e17b33729cca3bdd26b42a0Geert Uytterhoeven rambase += zcl->ramoffset; 2221e78bb882bf318bb41e17b33729cca3bdd26b42a0Geert Uytterhoeven } 22220e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven } else { 22230e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven struct zorro_dev *ram = zorro_find_device(zcl->ramid, NULL); 22240e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (!ram || !zorro_resource_len(ram)) { 22250e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven dev_err(info->device, "No video RAM found\n"); 22260e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven error = -ENODEV; 22270e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven goto err_release_fb; 22280e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven } 22290e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven rambase = zorro_resource_start(ram); 22300e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven ramsize = zorro_resource_len(ram); 223117bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven if (zcl->ramid2 && 223217bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven (ram = zorro_find_device(zcl->ramid2, NULL))) { 223317bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven if (zorro_resource_start(ram) != rambase + ramsize) { 223417bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven dev_warn(info->device, 223517bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven "Skipping non-contiguous RAM at %pR\n", 223617bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven &ram->resource); 223717bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven } else { 223817bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven ramsize += zorro_resource_len(ram); 223917bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven } 224017bdf48952d3f5c0be8137058f81d398d4606820Geert Uytterhoeven } 22410e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven } 22421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 22430e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven dev_info(info->device, 22440e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven "%s board detected, REG at 0x%lx, %lu MiB RAM at 0x%lx\n", 22450e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven cirrusfb_board_info[btype].name, regbase, ramsize / MB_, 22460e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven rambase); 22471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 22481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!zorro_request_device(z, "cirrusfb")) { 22490e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven dev_err(info->device, "Cannot reserve %pR\n", &z->resource); 22500e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven error = -EBUSY; 22511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds goto err_release_fb; 22521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 22531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 22540e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven cinfo = info->par; 22550e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven cinfo->btype = btype; 22561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 22570e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven info->fix.mmio_start = regbase; 22580e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024) 22596112ea0862facaeaeab504ee01c0d04bcd22daafGeert Uytterhoeven : ZTWO_VADDR(regbase); 22600e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (!cinfo->regbase) { 22610e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven dev_err(info->device, "Cannot map registers\n"); 22620e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven error = -EIO; 22630e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven goto err_release_dev; 22640e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven } 22651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 22660e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven info->fix.smem_start = rambase; 22670e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven info->screen_size = ramsize; 22680e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize) 22696112ea0862facaeaeab504ee01c0d04bcd22daafGeert Uytterhoeven : ZTWO_VADDR(rambase); 22700e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (!info->screen_base) { 22710e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven dev_err(info->device, "Cannot map video RAM\n"); 22720e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven error = -EIO; 22730e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven goto err_unmap_reg; 22741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 22750e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven 22761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cinfo->unmap = cirrusfb_zorro_unmap; 22771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 227875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_info(info->device, 22790e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven "Cirrus Logic chipset on Zorro bus, RAM (%lu MiB) at 0x%lx\n", 22800e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven ramsize / MB_, rambase); 22811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 22828f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt /* MCLK select etc. */ 22838f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt if (cirrusfb_board_info[btype].init_sr1f) 22848f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt vga_wseq(cinfo->regbase, CL_SEQR1F, 22858f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt cirrusfb_board_info[btype].sr1f); 22868f19e15b8ad23e28add5760ed049be2359f39fe8Krzysztof Helt 22870e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven error = cirrusfb_register(info); 22880e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (error) { 22890e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven dev_err(info->device, "Failed to register device, error %d\n", 22900e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven error); 22910e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven goto err_unmap_ram; 22920e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven } 2293bc5d8ac02f24d68efe8e267c96dd75c0531009abKrzysztof Helt 22940e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven zorro_set_drvdata(z, info); 22950e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven return 0; 2296bc5d8ac02f24d68efe8e267c96dd75c0531009abKrzysztof Helt 22970e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoevenerr_unmap_ram: 22980e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (rambase > 16 * MB_) 2299bc5d8ac02f24d68efe8e267c96dd75c0531009abKrzysztof Helt iounmap(info->screen_base); 23001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23010e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoevenerr_unmap_reg: 23020e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven if (regbase > 16 * MB_) 23030e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven iounmap(cinfo->regbase); 23040e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoevenerr_release_dev: 23050e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven zorro_release_device(z); 23061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldserr_release_fb: 23071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds framebuffer_release(info); 23080e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven return error; 23091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 23101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 231148c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartmanvoid cirrusfb_zorro_unregister(struct zorro_dev *z) 23121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 23131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds struct fb_info *info = zorro_get_drvdata(z); 23141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23158503df65976d0f845f49e8debff55c031635754eKrzysztof Helt cirrusfb_cleanup(info); 23160e0d13364b417a40266999c61671db0ef8690ad3Geert Uytterhoeven zorro_set_drvdata(z, NULL); 23171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 23181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic struct zorro_driver cirrusfb_zorro_driver = { 23201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .name = "cirrusfb", 23211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .id_table = cirrusfb_zorro_table, 23221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds .probe = cirrusfb_zorro_register, 232348c68c4f1b542444f175a9e136febcecf3e704d8Greg Kroah-Hartman .remove = cirrusfb_zorro_unregister, 23241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds}; 23251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CONFIG_ZORRO */ 23261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifndef MODULE 232875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Heltstatic int __init cirrusfb_setup(char *options) 232975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt{ 2330ee11940f8e7a2f064af22d52180cb5f9643eef61Vlada Peric char *this_opt; 23311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!options || !*options) 23331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 23341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23358503df65976d0f845f49e8debff55c031635754eKrzysztof Helt while ((this_opt = strsep(&options, ",")) != NULL) { 2336a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt if (!*this_opt) 2337a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt continue; 23381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!strcmp(this_opt, "noaccel")) 23401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds noaccel = 1; 2341a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt else if (!strncmp(this_opt, "mode:", 5)) 2342a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt mode_option = this_opt + 5; 2343a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt else 2344a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt mode_option = this_opt; 23451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 23461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 23471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 23481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 23491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 23511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Modularization 23521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 23531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>"); 23551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips"); 23561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus TorvaldsMODULE_LICENSE("GPL"); 23571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 235848c329e906f834711906ab4b0986ea0e857aff16Krzysztof Heltstatic int __init cirrusfb_init(void) 235948c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt{ 236048c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt int error = 0; 236148c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt 236248c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt#ifndef MODULE 236348c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt char *option = NULL; 236448c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt 236548c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt if (fb_get_options("cirrusfb", &option)) 236648c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt return -ENODEV; 236748c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt cirrusfb_setup(option); 236848c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt#endif 236948c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt 237048c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt#ifdef CONFIG_ZORRO 237148c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt error |= zorro_register_driver(&cirrusfb_zorro_driver); 237248c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt#endif 237348c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt#ifdef CONFIG_PCI 237448c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt error |= pci_register_driver(&cirrusfb_pci_driver); 237548c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt#endif 237648c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt return error; 237748c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt} 237848c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt 23798503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void __exit cirrusfb_exit(void) 23801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 23811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_PCI 23821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_unregister_driver(&cirrusfb_pci_driver); 23831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 23841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO 23851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds zorro_unregister_driver(&cirrusfb_zorro_driver); 23861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 23871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 23881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 23891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsmodule_init(cirrusfb_init); 23901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2391a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Heltmodule_param(mode_option, charp, 0); 2392a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof HeltMODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'"); 239355a0dd83eb24a89fd448006aaa9326df643861aeKrzysztof Heltmodule_param(noaccel, bool, 0); 239455a0dd83eb24a89fd448006aaa9326df643861aeKrzysztof HeltMODULE_PARM_DESC(noaccel, "Disable acceleration"); 2395a1d35a7a50d01b445e29d87f479f8c055a414f7eKrzysztof Helt 23961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef MODULE 23971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsmodule_exit(cirrusfb_exit); 23981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 23991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/**********************************************************************/ 24011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* about the following functions - I have used the same names for the */ 24021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* functions as Markus Wild did in his Retina driver for NetBSD as */ 24031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* they just made sense for this purpose. Apart from that, I wrote */ 24048503df65976d0f845f49e8debff55c031635754eKrzysztof Helt/* these functions myself. */ 24051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/**********************************************************************/ 24061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** WGen() - write into one of the external/general registers ***/ 24088503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WGen(const struct cirrusfb_info *cinfo, 24091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds int regnum, unsigned char val) 24101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 24111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long regofs = 0; 24121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO) { 24141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Picasso II specific hack */ 24158503df65976d0f845f49e8debff55c031635754eKrzysztof Helt/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || 24168503df65976d0f845f49e8debff55c031635754eKrzysztof Helt regnum == CL_VSSM2) */ 24171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D) 24181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds regofs = 0xfff; 24191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 24201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24218503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, regofs + regnum, val); 24221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 24231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** RGen() - read out one of the external/general registers ***/ 24258503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum) 24261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 24271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned long regofs = 0; 24281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO) { 24301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Picasso II specific hack */ 24318503df65976d0f845f49e8debff55c031635754eKrzysztof Helt/* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D || 24328503df65976d0f845f49e8debff55c031635754eKrzysztof Helt regnum == CL_VSSM2) */ 24331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D) 24341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds regofs = 0xfff; 24351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 24361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24378503df65976d0f845f49e8debff55c031635754eKrzysztof Helt return vga_r(cinfo->regbase, regofs + regnum); 24381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 24391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** AttrOn() - turn on VideoEnable for Attribute controller ***/ 24418503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void AttrOn(const struct cirrusfb_info *cinfo) 24421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 24438503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(cinfo != NULL); 24441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24458503df65976d0f845f49e8debff55c031635754eKrzysztof Helt if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) { 24461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* if we're just in "write value" mode, write back the */ 24471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* same value as before to not modify anything */ 24488503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, VGA_ATT_IW, 24498503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_r(cinfo->regbase, VGA_ATT_R)); 24501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 24511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* turn on video bit */ 24528503df65976d0f845f49e8debff55c031635754eKrzysztof Helt/* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */ 24538503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, VGA_ATT_IW, 0x33); 24541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* dummy write on Reg0 to be on "write index" mode next time */ 24568503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, VGA_ATT_IW, 0x00); 24571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 24581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** WHDR() - write into the Hidden DAC register ***/ 24601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* as the HDR is the only extension register that requires special treatment 24611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * (the other extension registers are accessible just like the "ordinary" 24621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * registers of their functional group) here is a specialized routine for 24631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * accessing the HDR 24641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 24658503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WHDR(const struct cirrusfb_info *cinfo, unsigned char val) 24661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 24671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char dummy; 24681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 246978d780e07247d52d3943b019bf9459bc9e95de1eKrzysztof Helt if (is_laguna(cinfo)) 24701b48cb563d59e03dbf530174f30c0ed3b6fba513Krzysztof Helt return; 24711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO) { 24721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Klaus' hint for correct access to HDR on some boards */ 24731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* first write 0 to pixel mask (3c6) */ 24748503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, VGA_PEL_MSK, 0x00); 24758503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 24761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* next read dummy from pixel address (3c8) */ 24778503df65976d0f845f49e8debff55c031635754eKrzysztof Helt dummy = RGen(cinfo, VGA_PEL_IW); 24788503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 24791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 24801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* now do the usual stuff to access the HDR */ 24811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24828503df65976d0f845f49e8debff55c031635754eKrzysztof Helt dummy = RGen(cinfo, VGA_PEL_MSK); 24838503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 24848503df65976d0f845f49e8debff55c031635754eKrzysztof Helt dummy = RGen(cinfo, VGA_PEL_MSK); 24858503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 24868503df65976d0f845f49e8debff55c031635754eKrzysztof Helt dummy = RGen(cinfo, VGA_PEL_MSK); 24878503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 24888503df65976d0f845f49e8debff55c031635754eKrzysztof Helt dummy = RGen(cinfo, VGA_PEL_MSK); 24898503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 24901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24918503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, VGA_PEL_MSK, val); 24928503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 24931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO) { 24951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* now first reset HDR access counter */ 24968503df65976d0f845f49e8debff55c031635754eKrzysztof Helt dummy = RGen(cinfo, VGA_PEL_IW); 24978503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 24981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 24991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* and at the end, restore the mask value */ 25001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* ## is this mask always 0xff? */ 25018503df65976d0f845f49e8debff55c031635754eKrzysztof Helt WGen(cinfo, VGA_PEL_MSK, 0xff); 25028503df65976d0f845f49e8debff55c031635754eKrzysztof Helt udelay(200); 25031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 25041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 25051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** WSFR() - write to the "special function register" (SFR) ***/ 25078503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WSFR(struct cirrusfb_info *cinfo, unsigned char val) 25081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 25091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO 25108503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(cinfo->regbase != NULL); 25111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cinfo->SFR = val; 25128503df65976d0f845f49e8debff55c031635754eKrzysztof Helt z_writeb(val, cinfo->regbase + 0x8000); 25131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 25141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 25151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* The Picasso has a second register for switching the monitor bit */ 25178503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WSFR2(struct cirrusfb_info *cinfo, unsigned char val) 25181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 25191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CONFIG_ZORRO 25201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* writing an arbitrary value to this one causes the monitor switcher */ 25211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* to flip to Amiga display */ 25228503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(cinfo->regbase != NULL); 25231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cinfo->SFR = val; 25248503df65976d0f845f49e8debff55c031635754eKrzysztof Helt z_writeb(val, cinfo->regbase + 0x9000); 25251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 25261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 25271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** WClut - set CLUT entry (range: 0..63) ***/ 25298503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red, 25301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char green, unsigned char blue) 25311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 25321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int data = VGA_PEL_D; 25331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* address write mode register is not translated.. */ 25358503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, VGA_PEL_IW, regnum); 25361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || 25381b48cb563d59e03dbf530174f30c0ed3b6fba513Krzysztof Helt cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 || 2539df3aafd57d590d6f3d95310fc3430f3a536d1e59Krzysztof Helt cinfo->btype == BT_SD64 || is_laguna(cinfo)) { 25401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* but DAC data register IS, at least for Picasso II */ 25411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO) 25421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds data += 0xfff; 25438503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, data, red); 25448503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, data, green); 25458503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, data, blue); 25461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 25478503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, data, blue); 25488503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, data, green); 25498503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, data, red); 25501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 25511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 25521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if 0 25541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/*** RClut - read CLUT entry (range 0..63) ***/ 25558503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red, 25561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char *green, unsigned char *blue) 25571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 25581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned int data = VGA_PEL_D; 25591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25608503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_w(cinfo->regbase, VGA_PEL_IR, regnum); 25611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || 25631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) { 25641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (cinfo->btype == BT_PICASSO) 25651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds data += 0xfff; 25668503df65976d0f845f49e8debff55c031635754eKrzysztof Helt *red = vga_r(cinfo->regbase, data); 25678503df65976d0f845f49e8debff55c031635754eKrzysztof Helt *green = vga_r(cinfo->regbase, data); 25688503df65976d0f845f49e8debff55c031635754eKrzysztof Helt *blue = vga_r(cinfo->regbase, data); 25691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 25708503df65976d0f845f49e8debff55c031635754eKrzysztof Helt *blue = vga_r(cinfo->regbase, data); 25718503df65976d0f845f49e8debff55c031635754eKrzysztof Helt *green = vga_r(cinfo->regbase, data); 25728503df65976d0f845f49e8debff55c031635754eKrzysztof Helt *red = vga_r(cinfo->regbase, data); 25731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 25741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 25751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 25761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/******************************************************************* 25781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cirrusfb_WaitBLT() 25791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds Wait for the BitBLT engine to complete a possible earlier job 25811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds*********************************************************************/ 25821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* FIXME: use interrupts instead */ 25848503df65976d0f845f49e8debff55c031635754eKrzysztof Heltstatic void cirrusfb_WaitBLT(u8 __iomem *regbase) 25851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 25868503df65976d0f845f49e8debff55c031635754eKrzysztof Helt while (vga_rgfx(regbase, CL_GR31) & 0x08) 258748c329e906f834711906ab4b0986ea0e857aff16Krzysztof Helt cpu_relax(); 25881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 25891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/******************************************************************* 25911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds cirrusfb_BitBLT() 25921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds perform accelerated "scrolling" 25941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds********************************************************************/ 25951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 25968343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Heltstatic void cirrusfb_set_blitter(u8 __iomem *regbase, 25978343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short nwidth, u_short nheight, 25988343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_long nsrc, u_long ndest, 25998343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short bltmode, u_short line_length) 26001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26018343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt{ 26021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* pitch: set to line_length */ 26038503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* dest pitch low */ 26048503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR24, line_length & 0xff); 26058503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* dest pitch hi */ 26068503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR25, line_length >> 8); 26078503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* source pitch low */ 26088503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR26, line_length & 0xff); 26098503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* source pitch hi */ 26108503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR27, line_length >> 8); 26111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* BLT width: actual number of pixels - 1 */ 26138503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT width low */ 26148503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR20, nwidth & 0xff); 26158503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT width hi */ 26168503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR21, nwidth >> 8); 26171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* BLT height: actual number of lines -1 */ 26198503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT height low */ 26208503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR22, nheight & 0xff); 26218503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT width hi */ 26228503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR23, nheight >> 8); 26231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* BLT destination */ 26258503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT dest low */ 26268503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff)); 26278503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT dest mid */ 26288503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8)); 26298503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT dest hi */ 26308503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16)); 26311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* BLT source */ 26338503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT src low */ 26348503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff)); 26358503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT src mid */ 26368503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8)); 26378503df65976d0f845f49e8debff55c031635754eKrzysztof Helt /* BLT src hi */ 26388503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16)); 26391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* BLT mode */ 26418503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */ 26421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* BLT ROP: SrcCopy */ 26448503df65976d0f845f49e8debff55c031635754eKrzysztof Helt vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */ 26451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* and finally: GO! */ 2647527410ff7fc5d45fe41523c0ba061113dea22017Krzysztof Helt vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */ 26481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 26491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/******************************************************************* 26518343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt cirrusfb_BitBLT() 26521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26538343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt perform accelerated "scrolling" 26541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds********************************************************************/ 26551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26568343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Heltstatic void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel, 26578343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short curx, u_short cury, 26588343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short destx, u_short desty, 26598343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short width, u_short height, 26608343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short line_length) 26611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 26628343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short nwidth = width - 1; 26638343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short nheight = height - 1; 26648343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_long nsrc, ndest; 26658343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_char bltmode; 26661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26678343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt bltmode = 0x00; 26688343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt /* if source adr < dest addr, do the Blt backwards */ 26698343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt if (cury <= desty) { 26708343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt if (cury == desty) { 26718343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt /* if src and dest are on the same line, check x */ 26728343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt if (curx < destx) 26738343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt bltmode |= 0x01; 26748343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt } else 26758343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt bltmode |= 0x01; 26768343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt } 26778343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt /* standard case: forward blitting */ 26788343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt nsrc = (cury * line_length) + curx; 26798343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt ndest = (desty * line_length) + destx; 26808343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt if (bltmode) { 26818343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt /* this means start addresses are at the end, 26828343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt * counting backwards 26838343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt */ 26848343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt nsrc += nheight * line_length + nwidth; 26858343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt ndest += nheight * line_length + nwidth; 26868343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt } 26871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26888503df65976d0f845f49e8debff55c031635754eKrzysztof Helt cirrusfb_WaitBLT(regbase); 26891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26908343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt cirrusfb_set_blitter(regbase, nwidth, nheight, 26918343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt nsrc, ndest, bltmode, line_length); 26928343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt} 26931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26948343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt/******************************************************************* 26958343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt cirrusfb_RectFill() 26961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 26978343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt perform accelerated rectangle fill 26988343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt********************************************************************/ 26991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27008343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Heltstatic void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel, 27018343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_short x, u_short y, u_short width, u_short height, 27029e848062533207130667f6eaa748549367ccbedfKrzysztof Helt u32 fg_color, u32 bg_color, u_short line_length, 27039e848062533207130667f6eaa748549367ccbedfKrzysztof Helt u_char blitmode) 27048343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt{ 27058343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_long ndest = (y * line_length) + x; 27068343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt u_char op; 27071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27088343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt cirrusfb_WaitBLT(regbase); 27091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* This is a ColorExpand Blt, using the */ 27111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* same color for foreground and background */ 27129e848062533207130667f6eaa748549367ccbedfKrzysztof Helt vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color); 27139e848062533207130667f6eaa748549367ccbedfKrzysztof Helt vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color); 27141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27159e848062533207130667f6eaa748549367ccbedfKrzysztof Helt op = 0x80; 27168343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt if (bits_per_pixel >= 16) { 27179e848062533207130667f6eaa748549367ccbedfKrzysztof Helt vga_wgfx(regbase, CL_GR10, bg_color >> 8); 27189e848062533207130667f6eaa748549367ccbedfKrzysztof Helt vga_wgfx(regbase, CL_GR11, fg_color >> 8); 27199e848062533207130667f6eaa748549367ccbedfKrzysztof Helt op = 0x90; 27208343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt } 27217cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt if (bits_per_pixel >= 24) { 27229e848062533207130667f6eaa748549367ccbedfKrzysztof Helt vga_wgfx(regbase, CL_GR12, bg_color >> 16); 27239e848062533207130667f6eaa748549367ccbedfKrzysztof Helt vga_wgfx(regbase, CL_GR13, fg_color >> 16); 27247cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt op = 0xa0; 27257cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt } 27267cade31cabec33c396b1dfd9c2842e793c2648efKrzysztof Helt if (bits_per_pixel == 32) { 27279e848062533207130667f6eaa748549367ccbedfKrzysztof Helt vga_wgfx(regbase, CL_GR14, bg_color >> 24); 27289e848062533207130667f6eaa748549367ccbedfKrzysztof Helt vga_wgfx(regbase, CL_GR15, fg_color >> 24); 27299e848062533207130667f6eaa748549367ccbedfKrzysztof Helt op = 0xb0; 27301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 27318343c89c4f1aac4fced7bb6919b0bdd0c13edcdcKrzysztof Helt cirrusfb_set_blitter(regbase, width - 1, height - 1, 27329e848062533207130667f6eaa748549367ccbedfKrzysztof Helt 0, ndest, op | blitmode, line_length); 27331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 27341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/************************************************************************** 27361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * bestclock() - determine closest possible clock lower(?) than the 27371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * desired pixel clock 27381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds **************************************************************************/ 2739dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Heltstatic void bestclock(long freq, int *nom, int *den, int *div) 27401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2741dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt int n, d; 2742dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt long h, diff; 27431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27448503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(nom != NULL); 27458503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(den != NULL); 27468503df65976d0f845f49e8debff55c031635754eKrzysztof Helt assert(div != NULL); 27471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *nom = 0; 27491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *den = 0; 27501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *div = 0; 27511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (freq < 8000) 27531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds freq = 8000; 27541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2755dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt diff = freq; 27561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for (n = 32; n < 128; n++) { 27587528f543889fd460964b42881296b2e84457684eKrzysztof Helt int s = 0; 27597528f543889fd460964b42881296b2e84457684eKrzysztof Helt 2760dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt d = (14318 * n) / freq; 27611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if ((d >= 7) && (d <= 63)) { 27627528f543889fd460964b42881296b2e84457684eKrzysztof Helt int temp = d; 27637528f543889fd460964b42881296b2e84457684eKrzysztof Helt 27647528f543889fd460964b42881296b2e84457684eKrzysztof Helt if (temp > 31) { 27657528f543889fd460964b42881296b2e84457684eKrzysztof Helt s = 1; 27667528f543889fd460964b42881296b2e84457684eKrzysztof Helt temp >>= 1; 27677528f543889fd460964b42881296b2e84457684eKrzysztof Helt } 27687528f543889fd460964b42881296b2e84457684eKrzysztof Helt h = ((14318 * n) / temp) >> s; 2769dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt h = h > freq ? h - freq : freq - h; 2770dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt if (h < diff) { 2771dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt diff = h; 27721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *nom = n; 27737528f543889fd460964b42881296b2e84457684eKrzysztof Helt *den = temp; 27747528f543889fd460964b42881296b2e84457684eKrzysztof Helt *div = s; 27751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 27761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 27777528f543889fd460964b42881296b2e84457684eKrzysztof Helt d++; 27781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if ((d >= 7) && (d <= 63)) { 27797528f543889fd460964b42881296b2e84457684eKrzysztof Helt if (d > 31) { 27807528f543889fd460964b42881296b2e84457684eKrzysztof Helt s = 1; 27817528f543889fd460964b42881296b2e84457684eKrzysztof Helt d >>= 1; 27827528f543889fd460964b42881296b2e84457684eKrzysztof Helt } 27837528f543889fd460964b42881296b2e84457684eKrzysztof Helt h = ((14318 * n) / d) >> s; 2784dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt h = h > freq ? h - freq : freq - h; 2785dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt if (h < diff) { 2786dafa32c5a1da19edca1d5c1b74d30d5d07b9befdKrzysztof Helt diff = h; 27871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *nom = n; 27887528f543889fd460964b42881296b2e84457684eKrzysztof Helt *den = d; 27897528f543889fd460964b42881296b2e84457684eKrzysztof Helt *div = s; 27901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 27911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 27921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 27931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 27941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* ------------------------------------------------------------------------- 27961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 27971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * debugging functions 27981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 27991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * ------------------------------------------------------------------------- 28001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 28011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 28021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#ifdef CIRRUSFB_DEBUG 28031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 28041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/** 28051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cirrusfb_dbg_print_regs 28061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @base: If using newmmio, the newmmio base address, otherwise %NULL 28071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @reg_class: type of registers to read: %CRT, or %SEQ 28081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 28091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * DESCRIPTION: 28101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Dumps the given list of VGA CRTC registers. If @base is %NULL, 28111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * old-style I/O ports are queried for information, otherwise MMIO is 28121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * used at the given @base address to query the information. 28131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 28141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 281575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Heltstatic void cirrusfb_dbg_print_regs(struct fb_info *info, 281675ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt caddr_t regbase, 281775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt enum cirrusfb_dbg_reg_class reg_class, ...) 28181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 28191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds va_list list; 28201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned char val = 0; 28211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds unsigned reg; 28221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds char *name; 28231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 28248503df65976d0f845f49e8debff55c031635754eKrzysztof Helt va_start(list, reg_class); 28251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 28268503df65976d0f845f49e8debff55c031635754eKrzysztof Helt name = va_arg(list, char *); 28271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds while (name != NULL) { 28288503df65976d0f845f49e8debff55c031635754eKrzysztof Helt reg = va_arg(list, int); 28291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 28301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds switch (reg_class) { 28311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case CRT: 28328503df65976d0f845f49e8debff55c031635754eKrzysztof Helt val = vga_rcrt(regbase, (unsigned char) reg); 28331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 28341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds case SEQ: 28358503df65976d0f845f49e8debff55c031635754eKrzysztof Helt val = vga_rseq(regbase, (unsigned char) reg); 28361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 28371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds default: 28381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* should never occur */ 2839c930faaed551aac898c618a7df1d68901ff244f0Richard Knutsson assert(false); 28401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds break; 28411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 28421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 284375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "%8s = 0x%02X\n", name, val); 28441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 28458503df65976d0f845f49e8debff55c031635754eKrzysztof Helt name = va_arg(list, char *); 28461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 28471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 28488503df65976d0f845f49e8debff55c031635754eKrzysztof Helt va_end(list); 28491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 28501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 28511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/** 28521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * cirrusfb_dbg_reg_dump 28531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * @base: If using newmmio, the newmmio base address, otherwise %NULL 28541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 28551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * DESCRIPTION: 28561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL, 28571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * old-style I/O ports are queried for information, otherwise MMIO is 28581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * used at the given @base address to query the information. 28591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 28601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 286175ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Heltstatic void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase) 28621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 286375ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "VGA CRTC register dump:\n"); 28641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 286575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt cirrusfb_dbg_print_regs(info, regbase, CRT, 28661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR00", 0x00, 28671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR01", 0x01, 28681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR02", 0x02, 28691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR03", 0x03, 28701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR04", 0x04, 28711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR05", 0x05, 28721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR06", 0x06, 28731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR07", 0x07, 28741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR08", 0x08, 28751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR09", 0x09, 28761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR0A", 0x0A, 28771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR0B", 0x0B, 28781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR0C", 0x0C, 28791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR0D", 0x0D, 28801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR0E", 0x0E, 28811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR0F", 0x0F, 28821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR10", 0x10, 28831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR11", 0x11, 28841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR12", 0x12, 28851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR13", 0x13, 28861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR14", 0x14, 28871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR15", 0x15, 28881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR16", 0x16, 28891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR17", 0x17, 28901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR18", 0x18, 28911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR22", 0x22, 28921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR24", 0x24, 28931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR26", 0x26, 28941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR2D", 0x2D, 28951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR2E", 0x2E, 28961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR2F", 0x2F, 28971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR30", 0x30, 28981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR31", 0x31, 28991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR32", 0x32, 29001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR33", 0x33, 29011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR34", 0x34, 29021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR35", 0x35, 29031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR36", 0x36, 29041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR37", 0x37, 29051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR38", 0x38, 29061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR39", 0x39, 29071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR3A", 0x3A, 29081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR3B", 0x3B, 29091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR3C", 0x3C, 29101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR3D", 0x3D, 29111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR3E", 0x3E, 29121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "CR3F", 0x3F, 29131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds NULL); 29141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 291575ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "\n"); 29161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 291775ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "VGA SEQ register dump:\n"); 29181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 291975ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt cirrusfb_dbg_print_regs(info, regbase, SEQ, 29201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR00", 0x00, 29211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR01", 0x01, 29221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR02", 0x02, 29231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR03", 0x03, 29241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR04", 0x04, 29251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR08", 0x08, 29261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR09", 0x09, 29271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR0A", 0x0A, 29281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR0B", 0x0B, 29291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR0D", 0x0D, 29301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR10", 0x10, 29311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR11", 0x11, 29321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR12", 0x12, 29331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR13", 0x13, 29341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR14", 0x14, 29351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR15", 0x15, 29361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR16", 0x16, 29371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR17", 0x17, 29381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR18", 0x18, 29391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR19", 0x19, 29401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR1A", 0x1A, 29411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR1B", 0x1B, 29421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR1C", 0x1C, 29431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR1D", 0x1D, 29441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR1E", 0x1E, 29451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds "SR1F", 0x1F, 29461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds NULL); 29471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 294875ed3a17a5bc0ecff5c256cfb81ed06f8a6fbb54Krzysztof Helt dev_dbg(info->device, "\n"); 29491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 29501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 29511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif /* CIRRUSFB_DEBUG */ 29521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2953