11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 21da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * linux/drivers/video/kyro/STG4000InitDevice.c 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 2000 Imagination Technologies Ltd 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 2002 STMicroelectronics 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This file is subject to the terms and conditions of the GNU General Public 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * License. See the file COPYING in the main directory of this archive 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * for more details. 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/kernel.h> 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/errno.h> 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/types.h> 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include <linux/pci.h> 161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#include "STG4000Reg.h" 18a0aa7d0639277f375989071fb52a7ce78beeef97Adrian Bunk#include "STG4000Interface.h" 191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* SDRAM fixed settings */ 211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SDRAM_CFG_0 0x49A1 221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SDRAM_CFG_1 0xA732 231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SDRAM_CFG_2 0x31 241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SDRAM_ARB_CFG 0xA0 251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define SDRAM_REFRESH 0x20 261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Reset values */ 281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_DAC_RST 0x0001 291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_C1_RST 0x0004 301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_C2_RST 0x0008 311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_3D_RST 0x0010 321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_VIDIN_RST 0x0020 331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_TLB_RST 0x0040 341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_SD_RST 0x0080 351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_VGA_RST 0x0100 361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_ROM_RST 0x0200 /* reserved bit, do not reset */ 371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_TA_RST 0x0400 381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_REG_RST 0x4000 391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PMX2_SOFTRESET_ALL 0x7fff 401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Core clock freq */ 421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CORE_PLL_FREQ 1000000 431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Reference Clock freq */ 451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define REF_FREQ 14318 461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PCI Registers */ 481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic u16 CorePllControl = 0x70; 491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define PCI_CONFIG_SUBSYS_ID 0x2e 511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* Misc */ 531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CORE_PLL_MODE_REG_0_7 3 541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CORE_PLL_MODE_REG_8_15 2 551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define CORE_PLL_MODE_CONFIG_REG 1 561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define DAC_PLL_CONFIG_REG 0 571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG_MAX_VCO 500000 591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG_MIN_VCO 100000 601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* PLL Clock */ 621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_SCALER 8 /* scale numbers by 2^8 for fixed point calc */ 631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MIN_R 2 /* Minimum multiplier */ 641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MAX_R 33 /* Max */ 651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MIN_F 2 /* Minimum divisor */ 661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MAX_F 513 /* Max */ 671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MIN_OD 0 /* Min output divider (shift) */ 681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MAX_OD 2 /* Max */ 691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */ 701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */ 711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */ 721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */ 731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */ 741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */ 751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */ 761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#define OS_DELAY(X) \ 781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ \ 791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsvolatile u32 i,count=0; \ 801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for(i=0;i<X;i++) count++; \ 811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsstatic u32 InitSDRAMRegisters(volatile STG4000REG __iomem *pSTGReg, 841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 dwSubSysID, u32 dwRevID) 851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 adwSDRAMArgCfg0[] = { 0xa0, 0x80, 0xa0, 0xa0, 0xa0 }; 871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 adwSDRAMCfg1[] = { 0x8732, 0x8732, 0xa732, 0xa732, 0x8732 }; 881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 adwSDRAMCfg2[] = { 0x87d2, 0x87d2, 0xa7d2, 0x87d2, 0xa7d2 }; 891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 adwSDRAMRsh[] = { 36, 39, 40 }; 901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 adwChipSpeed[] = { 110, 120, 125 }; 911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 dwMemTypeIdx; 921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 dwChipSpeedIdx; 931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Get memory tpye and chip speed indexs from the SubSysDevID */ 951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dwMemTypeIdx = (dwSubSysID & 0x70) >> 4; 961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds dwChipSpeedIdx = (dwSubSysID & 0x180) >> 7; 971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (dwMemTypeIdx > 4 || dwChipSpeedIdx > 2) 991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 1001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Program SD-RAM interface */ 1021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SDRAMArbiterConf, adwSDRAMArgCfg0[dwMemTypeIdx]); 1031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (dwRevID < 5) { 1041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SDRAMConf0, 0x49A1); 1051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg1[dwMemTypeIdx]); 1061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else { 1071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SDRAMConf0, 0x4DF1); 1081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg2[dwMemTypeIdx]); 1091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 1101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SDRAMConf2, 0x31); 1121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SDRAMRefresh, adwSDRAMRsh[dwChipSpeedIdx]); 1131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return adwChipSpeed[dwChipSpeedIdx] * 10000; 1151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 1161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsu32 ProgramClock(u32 refClock, 1181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 coreClock, 1191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 * FOut, u32 * ROut, u32 * POut) 1201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 1211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 R = 0, F = 0, OD = 0, ODIndex = 0; 1221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ulBestR = 0, ulBestF = 0, ulBestOD = 0; 1231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ulBestVCO = 0, ulBestClk = 0, ulBestScore = 0; 1241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ulScore, ulPhaseScore, ulVcoScore; 1251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ulTmp = 0, ulVCO; 1261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ulScaleClockReq, ulMinClock, ulMaxClock; 1271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ODValues[] = { 1, 2, 0 }; 1281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Translate clock in Hz */ 1301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds coreClock *= 100; /* in Hz */ 1311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds refClock *= 1000; /* in Hz */ 1321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Work out acceptable clock 1341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * The method calculates ~ +- 0.4% (1/256) 1351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulMinClock = coreClock - (coreClock >> 8); 1371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulMaxClock = coreClock + (coreClock >> 8); 1381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Scale clock required for use in calculations */ 1401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulScaleClockReq = coreClock >> STG4K3_PLL_SCALER; 1411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Iterate through post divider values */ 1431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds for (ODIndex = 0; ODIndex < 3; ODIndex++) { 1441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds OD = ODValues[ODIndex]; 1451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds R = STG4K3_PLL_MIN_R; 1461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* loop for pre-divider from min to max */ 1481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds while (R <= STG4K3_PLL_MAX_R) { 1491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* estimate required feedback multiplier */ 1501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulTmp = R * (ulScaleClockReq << OD); 1511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* F = ClkRequired * R * (2^OD) / Fref */ 1531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds F = (u32)(ulTmp / (refClock >> STG4K3_PLL_SCALER)); 1541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* compensate for accuracy */ 1561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (F > STG4K3_PLL_MIN_F) 1571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds F--; 1581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 1611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * We should be close to our target frequency (if it's 1621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * achievable with current OD & R) let's iterate 1631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * through F for best fit 1641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds while ((F >= STG4K3_PLL_MIN_F) && 1661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds (F <= STG4K3_PLL_MAX_F)) { 1671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Calc VCO at full accuracy */ 1681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulVCO = refClock / R; 1691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulVCO = F * ulVCO; 1701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 1721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Check it's within restricted VCO range 1731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * unless of course the desired frequency is 1741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * above the restricted range, then test 1751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * against VCO limit 1761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 1771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if ((ulVCO >= STG4K3_PLL_MINR_VCO) && 1781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ((ulVCO <= STG4K3_PLL_MAXR_VCO) || 1791da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ((coreClock > STG4K3_PLL_MAXR_VCO) 1801da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds && (ulVCO <= STG4K3_PLL_MAX_VCO)))) { 1811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulTmp = (ulVCO >> OD); /* Clock = VCO / (2^OD) */ 1821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Is this clock good enough? */ 1841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if ((ulTmp >= ulMinClock) 1851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds && (ulTmp <= ulMaxClock)) { 1861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K3_PLL_MAX_R)) >> 10); 1871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulVcoScore = ((ulVCO - STG4K3_PLL_MINR_VCO)) / ((STG4K3_PLL_MAXR_VCO - STG4K3_PLL_MINR_VCO) >> 10); 1891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulScore = ulPhaseScore + ulVcoScore; 1901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 1911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (!ulBestScore) { 1921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestVCO = ulVCO; 1931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestOD = OD; 1941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestF = F; 1951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestR = R; 1961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestClk = ulTmp; 1971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestScore = 1981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulScore; 1991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* is this better, ( aim for highest Score) */ 2011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /*-------------------------------------------------------------------------- 2021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds Here we want to use a scoring system which will take account of both the 2031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds value at the phase comparater and the VCO output 2041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds to do this we will use a cumulative score between the two 2051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds The way this ends up is that we choose the first value in the loop anyway 2061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds but we shall keep this code in case new restrictions come into play 2071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds --------------------------------------------------------------------------*/ 2081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if ((ulScore >= ulBestScore) && (OD > 0)) { 2091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestVCO = ulVCO; 2101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestOD = OD; 2111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestF = F; 2121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestR = R; 2131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestClk = ulTmp; 2141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulBestScore = 2151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulScore; 2161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds F++; 2201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds R++; 2221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* 2261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds did we find anything? 2271da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds Then return RFOD 2281da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2291da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (ulBestScore) { 2301da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *ROut = ulBestR; 2311da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *FOut = ulBestF; 2321da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2331da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if ((ulBestOD == 2) || (ulBestOD == 3)) { 2341da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *POut = 3; 2351da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } else 2361da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds *POut = ulBestOD; 2371da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2381da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds } 2391da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2401da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return (ulBestClk); 2411da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 2421da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2431da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvaldsint SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev) 2441da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds{ 2451da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 F, R, P; 2461da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u16 core_pll = 0, sub; 2471da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ulCoreClock; 2481da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 tmp; 2491da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds u32 ulChipSpeed; 2501da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2511da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(IntMask, 0xFFFF); 2521da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2531da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Disable Primary Core Thread0 */ 2541da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = STG_READ_REG(Thread0Enable); 2551da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds CLEAR_BIT(0); 2561da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(Thread0Enable, tmp); 2571da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2581da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Disable Primary Core Thread1 */ 2591da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = STG_READ_REG(Thread1Enable); 2601da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds CLEAR_BIT(0); 2611da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(Thread1Enable, tmp); 2621da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2631da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SoftwareReset, 2641da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST); 2651da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SoftwareReset, 2661da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST | 2671da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMX2_SOFTRESET_ROM_RST); 2681da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2691da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Need to play around to reset TA */ 2701da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(TAConfiguration, 0); 2711da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SoftwareReset, 2721da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST); 2731da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SoftwareReset, 2741da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST | 2751da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds PMX2_SOFTRESET_ROM_RST); 2761da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2771da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_read_config_word(pDev, PCI_CONFIG_SUBSYS_ID, &sub); 2781da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 27944c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok ulChipSpeed = InitSDRAMRegisters(pSTGReg, (u32)sub, 28044c10138fd4bbc4b6d6bff0873c24902f2a9da65Auke Kok (u32)pDev->revision); 2811da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2821da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds if (ulChipSpeed == 0) 2831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return -EINVAL; 2841da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2851da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ulCoreClock = ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P); 2861da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2871da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); 2881da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2891da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Set Core PLL Control to Core PLL Mode */ 2901da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2911da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Send bits 0:7 of the Core PLL Mode register */ 2921da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = ((CORE_PLL_MODE_REG_0_7 << 8) | (core_pll & 0x00FF)); 2931da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_word(pDev, CorePllControl, tmp); 2941da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Without some delay between the PCI config writes the clock does 2951da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds not reliably set when the code is compiled -O3 2961da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 2971da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds OS_DELAY(1000000); 2981da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 2991da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= SET_BIT(14); 3001da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_word(pDev, CorePllControl, tmp); 3011da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds OS_DELAY(1000000); 3021da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3031da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Send bits 8:15 of the Core PLL Mode register */ 3041da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = 3051da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds ((CORE_PLL_MODE_REG_8_15 << 8) | ((core_pll & 0xFF00) >> 8)); 3061da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_word(pDev, CorePllControl, tmp); 3071da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds OS_DELAY(1000000); 3081da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3091da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp |= SET_BIT(14); 3101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds pci_write_config_word(pDev, CorePllControl, tmp); 3111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds OS_DELAY(1000000); 3121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(SoftwareReset, PMX2_SOFTRESET_ALL); 3141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#if 0 3161da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Enable Primary Core Thread0 */ 3171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); 3181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(Thread0Enable, tmp); 3191da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3201da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds /* Enable Primary Core Thread1 */ 3211da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); 3221da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds STG_WRITE_REG(Thread1Enable, tmp); 3231da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds#endif 3241da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 3251da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds return 0; 3261da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds} 327