1/* 2 * linux/drivers/video/omap2/dss/dss.h 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#ifndef __OMAP2_DSS_H 24#define __OMAP2_DSS_H 25 26#include <linux/interrupt.h> 27 28#ifdef pr_fmt 29#undef pr_fmt 30#endif 31 32#ifdef DSS_SUBSYS_NAME 33#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt 34#else 35#define pr_fmt(fmt) fmt 36#endif 37 38#define DSSDBG(format, ...) \ 39 pr_debug(format, ## __VA_ARGS__) 40 41#ifdef DSS_SUBSYS_NAME 42#define DSSERR(format, ...) \ 43 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \ 44 ## __VA_ARGS__) 45#else 46#define DSSERR(format, ...) \ 47 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__) 48#endif 49 50#ifdef DSS_SUBSYS_NAME 51#define DSSINFO(format, ...) \ 52 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \ 53 ## __VA_ARGS__) 54#else 55#define DSSINFO(format, ...) \ 56 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__) 57#endif 58 59#ifdef DSS_SUBSYS_NAME 60#define DSSWARN(format, ...) \ 61 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \ 62 ## __VA_ARGS__) 63#else 64#define DSSWARN(format, ...) \ 65 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__) 66#endif 67 68/* OMAP TRM gives bitfields as start:end, where start is the higher bit 69 number. For example 7:0 */ 70#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 71#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 72#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) 73#define FLD_MOD(orig, val, start, end) \ 74 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 75 76enum dss_io_pad_mode { 77 DSS_IO_PAD_MODE_RESET, 78 DSS_IO_PAD_MODE_RFBI, 79 DSS_IO_PAD_MODE_BYPASS, 80}; 81 82enum dss_hdmi_venc_clk_source_select { 83 DSS_VENC_TV_CLK = 0, 84 DSS_HDMI_M_PCLK = 1, 85}; 86 87enum dss_dsi_content_type { 88 DSS_DSI_CONTENT_DCS, 89 DSS_DSI_CONTENT_GENERIC, 90}; 91 92enum dss_writeback_channel { 93 DSS_WB_LCD1_MGR = 0, 94 DSS_WB_LCD2_MGR = 1, 95 DSS_WB_TV_MGR = 2, 96 DSS_WB_OVL0 = 3, 97 DSS_WB_OVL1 = 4, 98 DSS_WB_OVL2 = 5, 99 DSS_WB_OVL3 = 6, 100 DSS_WB_LCD3_MGR = 7, 101}; 102 103struct dispc_clock_info { 104 /* rates that we get with dividers below */ 105 unsigned long lck; 106 unsigned long pck; 107 108 /* dividers */ 109 u16 lck_div; 110 u16 pck_div; 111}; 112 113struct dsi_clock_info { 114 /* rates that we get with dividers below */ 115 unsigned long fint; 116 unsigned long clkin4ddr; 117 unsigned long clkin; 118 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK 119 * OMAP4: PLLx_CLK1 */ 120 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK 121 * OMAP4: PLLx_CLK2 */ 122 unsigned long lp_clk; 123 124 /* dividers */ 125 u16 regn; 126 u16 regm; 127 u16 regm_dispc; /* OMAP3: REGM3 128 * OMAP4: REGM4 */ 129 u16 regm_dsi; /* OMAP3: REGM4 130 * OMAP4: REGM5 */ 131 u16 lp_clk_div; 132}; 133 134struct dss_lcd_mgr_config { 135 enum dss_io_pad_mode io_pad_mode; 136 137 bool stallmode; 138 bool fifohandcheck; 139 140 struct dispc_clock_info clock_info; 141 142 int video_port_width; 143 144 int lcden_sig_polarity; 145}; 146 147struct seq_file; 148struct platform_device; 149 150/* core */ 151struct platform_device *dss_get_core_pdev(void); 152int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask); 153void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask); 154int dss_set_min_bus_tput(struct device *dev, unsigned long tput); 155int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); 156 157/* display */ 158int dss_suspend_all_devices(void); 159int dss_resume_all_devices(void); 160void dss_disable_all_devices(void); 161 162int display_init_sysfs(struct platform_device *pdev); 163void display_uninit_sysfs(struct platform_device *pdev); 164 165/* manager */ 166int dss_init_overlay_managers(void); 167void dss_uninit_overlay_managers(void); 168int dss_init_overlay_managers_sysfs(struct platform_device *pdev); 169void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev); 170int dss_mgr_simple_check(struct omap_overlay_manager *mgr, 171 const struct omap_overlay_manager_info *info); 172int dss_mgr_check_timings(struct omap_overlay_manager *mgr, 173 const struct omap_video_timings *timings); 174int dss_mgr_check(struct omap_overlay_manager *mgr, 175 struct omap_overlay_manager_info *info, 176 const struct omap_video_timings *mgr_timings, 177 const struct dss_lcd_mgr_config *config, 178 struct omap_overlay_info **overlay_infos); 179 180static inline bool dss_mgr_is_lcd(enum omap_channel id) 181{ 182 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 || 183 id == OMAP_DSS_CHANNEL_LCD3) 184 return true; 185 else 186 return false; 187} 188 189int dss_manager_kobj_init(struct omap_overlay_manager *mgr, 190 struct platform_device *pdev); 191void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr); 192 193/* overlay */ 194void dss_init_overlays(struct platform_device *pdev); 195void dss_uninit_overlays(struct platform_device *pdev); 196void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr); 197int dss_ovl_simple_check(struct omap_overlay *ovl, 198 const struct omap_overlay_info *info); 199int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info, 200 const struct omap_video_timings *mgr_timings); 201bool dss_ovl_use_replication(struct dss_lcd_mgr_config config, 202 enum omap_color_mode mode); 203int dss_overlay_kobj_init(struct omap_overlay *ovl, 204 struct platform_device *pdev); 205void dss_overlay_kobj_uninit(struct omap_overlay *ovl); 206 207/* DSS */ 208int dss_init_platform_driver(void) __init; 209void dss_uninit_platform_driver(void); 210 211unsigned long dss_get_dispc_clk_rate(void); 212int dss_dpi_select_source(enum omap_channel channel); 213void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); 214enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void); 215const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src); 216void dss_dump_clocks(struct seq_file *s); 217 218#if defined(CONFIG_OMAP2_DSS_DEBUGFS) 219void dss_debug_dump_clocks(struct seq_file *s); 220#endif 221 222void dss_sdi_init(int datapairs); 223int dss_sdi_enable(void); 224void dss_sdi_disable(void); 225 226void dss_select_dsi_clk_source(int dsi_module, 227 enum omap_dss_clk_source clk_src); 228void dss_select_lcd_clk_source(enum omap_channel channel, 229 enum omap_dss_clk_source clk_src); 230enum omap_dss_clk_source dss_get_dispc_clk_source(void); 231enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module); 232enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); 233 234void dss_set_venc_output(enum omap_dss_venc_type type); 235void dss_set_dac_pwrdn_bgz(bool enable); 236 237int dss_set_fck_rate(unsigned long rate); 238 239typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); 240bool dss_div_calc(unsigned long pck, unsigned long fck_min, 241 dss_div_calc_func func, void *data); 242 243/* SDI */ 244int sdi_init_platform_driver(void) __init; 245void sdi_uninit_platform_driver(void) __exit; 246 247int sdi_init_port(struct platform_device *pdev, struct device_node *port) __init; 248void sdi_uninit_port(void) __exit; 249 250/* DSI */ 251 252typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint, 253 unsigned long pll, void *data); 254typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc, 255 void *data); 256 257#ifdef CONFIG_OMAP2_DSS_DSI 258 259struct dentry; 260struct file_operations; 261 262int dsi_init_platform_driver(void) __init; 263void dsi_uninit_platform_driver(void) __exit; 264 265int dsi_runtime_get(struct platform_device *dsidev); 266void dsi_runtime_put(struct platform_device *dsidev); 267 268void dsi_dump_clocks(struct seq_file *s); 269 270void dsi_irq_handler(void); 271u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt); 272 273unsigned long dsi_get_pll_clkin(struct platform_device *dsidev); 274 275bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll, 276 unsigned long out_min, dsi_hsdiv_calc_func func, void *data); 277bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin, 278 unsigned long pll_min, unsigned long pll_max, 279 dsi_pll_calc_func func, void *data); 280 281unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev); 282int dsi_pll_set_clock_div(struct platform_device *dsidev, 283 struct dsi_clock_info *cinfo); 284int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, 285 bool enable_hsdiv); 286void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes); 287void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev); 288void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev); 289struct platform_device *dsi_get_dsidev_from_id(int module); 290#else 291static inline int dsi_runtime_get(struct platform_device *dsidev) 292{ 293 return 0; 294} 295static inline void dsi_runtime_put(struct platform_device *dsidev) 296{ 297} 298static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 299{ 300 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__); 301 return 0; 302} 303static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) 304{ 305 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__); 306 return 0; 307} 308static inline int dsi_pll_set_clock_div(struct platform_device *dsidev, 309 struct dsi_clock_info *cinfo) 310{ 311 WARN("%s: DSI not compiled in\n", __func__); 312 return -ENODEV; 313} 314static inline int dsi_pll_init(struct platform_device *dsidev, 315 bool enable_hsclk, bool enable_hsdiv) 316{ 317 WARN("%s: DSI not compiled in\n", __func__); 318 return -ENODEV; 319} 320static inline void dsi_pll_uninit(struct platform_device *dsidev, 321 bool disconnect_lanes) 322{ 323} 324static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev) 325{ 326} 327static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev) 328{ 329} 330static inline struct platform_device *dsi_get_dsidev_from_id(int module) 331{ 332 return NULL; 333} 334 335static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev) 336{ 337 return 0; 338} 339 340static inline bool dsi_hsdiv_calc(struct platform_device *dsidev, 341 unsigned long pll, unsigned long out_min, 342 dsi_hsdiv_calc_func func, void *data) 343{ 344 return false; 345} 346 347static inline bool dsi_pll_calc(struct platform_device *dsidev, 348 unsigned long clkin, 349 unsigned long pll_min, unsigned long pll_max, 350 dsi_pll_calc_func func, void *data) 351{ 352 return false; 353} 354 355#endif 356 357/* DPI */ 358int dpi_init_platform_driver(void) __init; 359void dpi_uninit_platform_driver(void) __exit; 360 361int dpi_init_port(struct platform_device *pdev, struct device_node *port) __init; 362void dpi_uninit_port(void) __exit; 363 364/* DISPC */ 365int dispc_init_platform_driver(void) __init; 366void dispc_uninit_platform_driver(void) __exit; 367void dispc_dump_clocks(struct seq_file *s); 368 369void dispc_enable_sidle(void); 370void dispc_disable_sidle(void); 371 372void dispc_lcd_enable_signal(bool enable); 373void dispc_pck_free_enable(bool enable); 374void dispc_enable_fifomerge(bool enable); 375void dispc_enable_gamma_table(bool enable); 376void dispc_set_loadmode(enum omap_dss_load_mode mode); 377 378typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck, 379 unsigned long pck, void *data); 380bool dispc_div_calc(unsigned long dispc, 381 unsigned long pck_min, unsigned long pck_max, 382 dispc_div_calc_func func, void *data); 383 384bool dispc_mgr_timings_ok(enum omap_channel channel, 385 const struct omap_video_timings *timings); 386unsigned long dispc_fclk_rate(void); 387int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 388 struct dispc_clock_info *cinfo); 389 390 391void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high); 392void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, 393 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 394 bool manual_update); 395 396unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 397unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 398unsigned long dispc_core_clk_rate(void); 399void dispc_mgr_set_clock_div(enum omap_channel channel, 400 const struct dispc_clock_info *cinfo); 401int dispc_mgr_get_clock_div(enum omap_channel channel, 402 struct dispc_clock_info *cinfo); 403void dispc_set_tv_pclk(unsigned long pclk); 404 405u32 dispc_wb_get_framedone_irq(void); 406bool dispc_wb_go_busy(void); 407void dispc_wb_go(void); 408void dispc_wb_enable(bool enable); 409bool dispc_wb_is_enabled(void); 410void dispc_wb_set_channel_in(enum dss_writeback_channel channel); 411int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 412 bool mem_to_mem, const struct omap_video_timings *timings); 413 414/* VENC */ 415int venc_init_platform_driver(void) __init; 416void venc_uninit_platform_driver(void) __exit; 417 418/* HDMI */ 419int hdmi4_init_platform_driver(void) __init; 420void hdmi4_uninit_platform_driver(void) __exit; 421 422int hdmi5_init_platform_driver(void) __init; 423void hdmi5_uninit_platform_driver(void) __exit; 424 425/* RFBI */ 426int rfbi_init_platform_driver(void) __init; 427void rfbi_uninit_platform_driver(void) __exit; 428 429 430#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 431static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) 432{ 433 int b; 434 for (b = 0; b < 32; ++b) { 435 if (irqstatus & (1 << b)) 436 irq_arr[b]++; 437 } 438} 439#endif 440 441#endif 442