1b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/* 2b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * include/linux/amba/pl022.h 3b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * 4b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * Copyright (C) 2008-2009 ST-Ericsson AB 5b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * Copyright (C) 2006 STMicroelectronics Pvt. Ltd. 6b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * 7b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * Author: Linus Walleij <linus.walleij@stericsson.com> 8b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * 9b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * Initial version inspired by: 10b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c 11b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * Initial adoption to PL022 by: 12b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * Sachin Verma <sachin.verma@st.com> 13b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * 14b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * This program is free software; you can redistribute it and/or modify 15b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * it under the terms of the GNU General Public License as published by 16b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * the Free Software Foundation; either version 2 of the License, or 17b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * (at your option) any later version. 18b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * 19b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * This program is distributed in the hope that it will be useful, 20b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * but WITHOUT ANY WARRANTY; without even the implied warranty of 21b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * GNU General Public License for more details. 23b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 24b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 25b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij#ifndef _SSP_PL022_H 26b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij#define _SSP_PL022_H 27b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 28327ef2e9048a5e39bf84d7f17f78a87e7a068742Viresh Kumar#include <linux/types.h> 29327ef2e9048a5e39bf84d7f17f78a87e7a068742Viresh Kumar 30b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 31b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * whether SSP is in loopback mode or not 32b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 33b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_loopback { 34b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij LOOPBACK_DISABLED, 35b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij LOOPBACK_ENABLED 36b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 37b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 38b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 39b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum ssp_interface - interfaces allowed for this SSP Controller 40b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface 41b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial 42b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * interface 43b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire 44b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * interface 45b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810 46b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * &STn8815 only) 47b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 48b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_interface { 49b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_INTERFACE_MOTOROLA_SPI, 50b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_INTERFACE_TI_SYNC_SERIAL, 51b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_INTERFACE_NATIONAL_MICROWIRE, 52b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_INTERFACE_UNIDIRECTIONAL 53b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 54b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 55b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 56b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum ssp_hierarchy - whether SSP is configured as Master or Slave 57b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 58b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_hierarchy { 59b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_MASTER, 60b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_SLAVE 61b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 62b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 63b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 64b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum ssp_clock_params - clock parameters, to set SSP clock at a 65b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * desired freq 66b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 67b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijstruct ssp_clock_params { 68b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij u8 cpsdvsr; /* value from 2 to 254 (even only!) */ 69b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij u8 scr; /* value from 0 to 255 */ 70b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 71b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 72b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 73b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum ssp_rx_endian - endianess of Rx FIFO Data 74556f4aeb7d9dfac8573d0281dd555bd3210d8366Linus Walleij * this feature is only available in ST versionf of PL022 75b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 76b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_rx_endian { 77b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_RX_MSB, 78b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_RX_LSB 79b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 80b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 81b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 82b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum ssp_tx_endian - endianess of Tx FIFO Data 83b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 84b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_tx_endian { 85b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_TX_MSB, 86b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_TX_LSB 87b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 88b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 89b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 90b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum ssp_data_size - number of bits in one data element 91b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 92b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_data_size { 93b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6, 94b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9, 95b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12, 96b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15, 97b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18, 98b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21, 99b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24, 100b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27, 101b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30, 102b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_DATA_BITS_31, SSP_DATA_BITS_32 103b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 104b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 105b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 106b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum ssp_mode - SSP mode of operation (Communication modes) 107b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 108b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_mode { 109b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij INTERRUPT_TRANSFER, 110b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij POLLING_TRANSFER, 111b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij DMA_TRANSFER 112b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 113b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 114b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 115b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum ssp_rx_level_trig - receive FIFO watermark level which triggers 116b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * IT: Interrupt fires when _N_ or more elements in RX FIFO. 117b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 118b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_rx_level_trig { 119b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_RX_1_OR_MORE_ELEM, 120b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_RX_4_OR_MORE_ELEM, 121b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_RX_8_OR_MORE_ELEM, 122b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_RX_16_OR_MORE_ELEM, 123b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_RX_32_OR_MORE_ELEM 124b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 125b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 126b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 127b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * Transmit FIFO watermark level which triggers (IT Interrupt fires 128b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * when _N_ or more empty locations in TX FIFO) 129b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 130b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_tx_level_trig { 131b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_TX_1_OR_MORE_EMPTY_LOC, 132b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_TX_4_OR_MORE_EMPTY_LOC, 133b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_TX_8_OR_MORE_EMPTY_LOC, 134b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_TX_16_OR_MORE_EMPTY_LOC, 135b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_TX_32_OR_MORE_EMPTY_LOC 136b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 137b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 138b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 139b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum SPI Clock Phase - clock phase (Motorola SPI interface only) 140ee2b805c8eb6459cf541ef141ff70dae17af59caLinus Walleij * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity) 141ee2b805c8eb6459cf541ef141ff70dae17af59caLinus Walleij * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity) 142b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 143b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_spi_clk_phase { 144ee2b805c8eb6459cf541ef141ff70dae17af59caLinus Walleij SSP_CLK_FIRST_EDGE, 145ee2b805c8eb6459cf541ef141ff70dae17af59caLinus Walleij SSP_CLK_SECOND_EDGE 146b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 147b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 148b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 149b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only) 150b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_CLK_POL_IDLE_LOW: Low inactive level 151b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_CLK_POL_IDLE_HIGH: High inactive level 152b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 153b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_spi_clk_pol { 154b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_CLK_POL_IDLE_LOW, 155b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_CLK_POL_IDLE_HIGH 156b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 157b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 158b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 159b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * Microwire Conrol Lengths Command size in microwire format 160b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 161b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_microwire_ctrl_len { 162b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6, 163b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_7, SSP_BITS_8, SSP_BITS_9, 164b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_10, SSP_BITS_11, SSP_BITS_12, 165b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_13, SSP_BITS_14, SSP_BITS_15, 166b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_16, SSP_BITS_17, SSP_BITS_18, 167b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_19, SSP_BITS_20, SSP_BITS_21, 168b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_22, SSP_BITS_23, SSP_BITS_24, 169b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_25, SSP_BITS_26, SSP_BITS_27, 170b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_28, SSP_BITS_29, SSP_BITS_30, 171b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_BITS_31, SSP_BITS_32 172b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 173b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 174b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 175b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * enum Microwire Wait State 176b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit 177b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit 178b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 179b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_microwire_wait_state { 180b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_MWIRE_WAIT_ZERO, 181b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_MWIRE_WAIT_ONE 182b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 183b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 184b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 185781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * enum ssp_duplex - whether Full/Half Duplex on microwire, only 186781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * available in the ST Micro variant. 187b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional, 188b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * SSPRXD not used 189b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is 190b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * an input. 191b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 192b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_duplex { 193b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, 194b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_MICROWIRE_CHANNEL_HALF_DUPLEX 195b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 196b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 197b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 198781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * enum ssp_clkdelay - an optional clock delay on the feedback clock 199781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * only available in the ST Micro PL023 variant. 200781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the 201781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * slave is sampled directly 202781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with 203781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * a delay of T-dt 204781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt 205781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt 206781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt 207781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt 208781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt 209781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt 210781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij */ 211781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleijenum ssp_clkdelay { 212781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij SSP_FEEDBACK_CLK_DELAY_NONE, 213781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij SSP_FEEDBACK_CLK_DELAY_1T, 214781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij SSP_FEEDBACK_CLK_DELAY_2T, 215781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij SSP_FEEDBACK_CLK_DELAY_3T, 216781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij SSP_FEEDBACK_CLK_DELAY_4T, 217781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij SSP_FEEDBACK_CLK_DELAY_5T, 218781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij SSP_FEEDBACK_CLK_DELAY_6T, 219781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij SSP_FEEDBACK_CLK_DELAY_7T 220781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij}; 221781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij 222781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij/** 223b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * CHIP select/deselect commands 224b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 225b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijenum ssp_chip_select { 226b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_CHIP_SELECT, 227b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij SSP_CHIP_DESELECT 228b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 229b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 230b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 231b1b6b9aa6fd32db97469e65d301ebc32dcd67992Linus Walleijstruct dma_chan; 232b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 233b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * struct pl022_ssp_master - device.platform_data for SPI controller devices. 2345b063b87deba33ed1676db9d16c52ede662132d8Alexandre Pereira da Silva * @bus_id: identifier for this bus 235b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @num_chipselect: chipselects are used to distinguish individual 236b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * SPI slaves, and are numbered from zero to num_chipselects - 1. 237b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * each slave has a chipselect signal, but it's common that not 238b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * every chipselect is connected to a slave. 239b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @enable_dma: if true enables DMA driven transfers. 240b1b6b9aa6fd32db97469e65d301ebc32dcd67992Linus Walleij * @dma_rx_param: parameter to locate an RX DMA channel. 241b1b6b9aa6fd32db97469e65d301ebc32dcd67992Linus Walleij * @dma_tx_param: parameter to locate a TX DMA channel. 24253e4acea0e819a6a8513e10a0773f2259ede0481Chris Blair * @autosuspend_delay: delay in ms following transfer completion before the 24353e4acea0e819a6a8513e10a0773f2259ede0481Chris Blair * runtime power management system suspends the device. A setting of 0 24453e4acea0e819a6a8513e10a0773f2259ede0481Chris Blair * indicates no delay and the device will be suspended immediately. 24514af60b6fb3b76634278364b697dae2f9f360abfChris Blair * @rt: indicates the controller should run the message pump with realtime 24614af60b6fb3b76634278364b697dae2f9f360abfChris Blair * priority to minimise the transfer latency on the bus. 247f6f46de1063c8829713cd9d5b960dd8cb66cde8bRoland Stigge * @chipselects: list of <num_chipselects> chip select gpios 248b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 249b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijstruct pl022_ssp_controller { 250b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij u16 bus_id; 251b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij u8 num_chipselect; 252b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij u8 enable_dma:1; 253b1b6b9aa6fd32db97469e65d301ebc32dcd67992Linus Walleij bool (*dma_filter)(struct dma_chan *chan, void *filter_param); 254b1b6b9aa6fd32db97469e65d301ebc32dcd67992Linus Walleij void *dma_rx_param; 255b1b6b9aa6fd32db97469e65d301ebc32dcd67992Linus Walleij void *dma_tx_param; 25653e4acea0e819a6a8513e10a0773f2259ede0481Chris Blair int autosuspend_delay; 25714af60b6fb3b76634278364b697dae2f9f360abfChris Blair bool rt; 258f6f46de1063c8829713cd9d5b960dd8cb66cde8bRoland Stigge int *chipselects; 259b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 260b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 261b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij/** 262b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * struct ssp_config_chip - spi_board_info.controller_data for SPI 263b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * slave devices, copied to spi_device.controller_data. 264b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * 265b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @iface: Interface type(Motorola, TI, Microwire, Universal) 266b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @hierarchy: sets whether interface is master or slave 267b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @slave_tx_disable: SSPTXD is disconnected (in slave mode only) 268b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @clk_freq: Tune freq parameters of SSP(when in master mode) 269b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @com_mode: communication mode: polling, Interrupt or DMA 270b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode) 271b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode) 272b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @ctrl_len: Microwire interface: Control length 273b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @wait_state: Microwire interface: Wait state 274b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @duplex: Microwire interface: Full/Half duplex 275781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * @clkdelay: on the PL023 variant, the delay in feeback clock cycles 276781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij * before sampling the incoming line 277b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * @cs_control: function pointer to board-specific function to 278b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij * assert/deassert I/O port to control HW generation of devices chip-select. 279b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij */ 280b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleijstruct pl022_config_chip { 281b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij enum ssp_interface iface; 282b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij enum ssp_hierarchy hierarchy; 283b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij bool slave_tx_disable; 284b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij struct ssp_clock_params clk_freq; 285b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij enum ssp_mode com_mode; 286b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij enum ssp_rx_level_trig rx_lev_trig; 287b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij enum ssp_tx_level_trig tx_lev_trig; 288b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij enum ssp_microwire_ctrl_len ctrl_len; 289b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij enum ssp_microwire_wait_state wait_state; 290b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij enum ssp_duplex duplex; 291781c7b129b1beb876905f7212927aa0ee1b022e5Linus Walleij enum ssp_clkdelay clkdelay; 292b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij void (*cs_control) (u32 control); 293b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij}; 294b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij 295b43d65f7e818485664037a46367cfb15af05bd8cLinus Walleij#endif /* _SSP_PL022_H */ 296