clk-provider.h revision 045779942c04646a222289989e6a5b617dfdedf7
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15 16#ifdef CONFIG_COMMON_CLK 17 18/* 19 * flags used across common struct clk. these flags should only affect the 20 * top-level framework. custom flags for dealing with hardware specifics 21 * belong in struct clk_foo 22 */ 23#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 24#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 25#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 26#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 28#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 29#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 30 31struct clk_hw; 32 33/** 34 * struct clk_ops - Callback operations for hardware clocks; these are to 35 * be provided by the clock implementation, and will be called by drivers 36 * through the clk_* api. 37 * 38 * @prepare: Prepare the clock for enabling. This must not return until 39 * the clock is fully prepared, and it's safe to call clk_enable. 40 * This callback is intended to allow clock implementations to 41 * do any initialisation that may sleep. Called with 42 * prepare_lock held. 43 * 44 * @unprepare: Release the clock from its prepared state. This will typically 45 * undo any work done in the @prepare callback. Called with 46 * prepare_lock held. 47 * 48 * @is_prepared: Queries the hardware to determine if the clock is prepared. 49 * This function is allowed to sleep. Optional, if this op is not 50 * set then the prepare count will be used. 51 * 52 * @unprepare_unused: Unprepare the clock atomically. Only called from 53 * clk_disable_unused for prepare clocks with special needs. 54 * Called with prepare mutex held. This function may sleep. 55 * 56 * @enable: Enable the clock atomically. This must not return until the 57 * clock is generating a valid clock signal, usable by consumer 58 * devices. Called with enable_lock held. This function must not 59 * sleep. 60 * 61 * @disable: Disable the clock atomically. Called with enable_lock held. 62 * This function must not sleep. 63 * 64 * @is_enabled: Queries the hardware to determine if the clock is enabled. 65 * This function must not sleep. Optional, if this op is not 66 * set then the enable count will be used. 67 * 68 * @disable_unused: Disable the clock atomically. Only called from 69 * clk_disable_unused for gate clocks with special needs. 70 * Called with enable_lock held. This function must not 71 * sleep. 72 * 73 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 74 * parent rate is an input parameter. It is up to the caller to 75 * ensure that the prepare_mutex is held across this call. 76 * Returns the calculated rate. Optional, but recommended - if 77 * this op is not set then clock rate will be initialized to 0. 78 * 79 * @round_rate: Given a target rate as input, returns the closest rate actually 80 * supported by the clock. 81 * 82 * @get_parent: Queries the hardware to determine the parent of a clock. The 83 * return value is a u8 which specifies the index corresponding to 84 * the parent clock. This index can be applied to either the 85 * .parent_names or .parents arrays. In short, this function 86 * translates the parent value read from hardware into an array 87 * index. Currently only called when the clock is initialized by 88 * __clk_init. This callback is mandatory for clocks with 89 * multiple parents. It is optional (and unnecessary) for clocks 90 * with 0 or 1 parents. 91 * 92 * @set_parent: Change the input source of this clock; for clocks with multiple 93 * possible parents specify a new parent by passing in the index 94 * as a u8 corresponding to the parent in either the .parent_names 95 * or .parents arrays. This function in affect translates an 96 * array index into the value programmed into the hardware. 97 * Returns 0 on success, -EERROR otherwise. 98 * 99 * @set_rate: Change the rate of this clock. The requested rate is specified 100 * by the second argument, which should typically be the return 101 * of .round_rate call. The third argument gives the parent rate 102 * which is likely helpful for most .set_rate implementation. 103 * Returns 0 on success, -EERROR otherwise. 104 * 105 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 106 * implementations to split any work between atomic (enable) and sleepable 107 * (prepare) contexts. If enabling a clock requires code that might sleep, 108 * this must be done in clk_prepare. Clock enable code that will never be 109 * called in a sleepable context may be implemented in clk_enable. 110 * 111 * Typically, drivers will call clk_prepare when a clock may be needed later 112 * (eg. when a device is opened), and clk_enable when the clock is actually 113 * required (eg. from an interrupt). Note that clk_prepare MUST have been 114 * called before clk_enable. 115 */ 116struct clk_ops { 117 int (*prepare)(struct clk_hw *hw); 118 void (*unprepare)(struct clk_hw *hw); 119 int (*is_prepared)(struct clk_hw *hw); 120 void (*unprepare_unused)(struct clk_hw *hw); 121 int (*enable)(struct clk_hw *hw); 122 void (*disable)(struct clk_hw *hw); 123 int (*is_enabled)(struct clk_hw *hw); 124 void (*disable_unused)(struct clk_hw *hw); 125 unsigned long (*recalc_rate)(struct clk_hw *hw, 126 unsigned long parent_rate); 127 long (*round_rate)(struct clk_hw *hw, unsigned long, 128 unsigned long *); 129 int (*set_parent)(struct clk_hw *hw, u8 index); 130 u8 (*get_parent)(struct clk_hw *hw); 131 int (*set_rate)(struct clk_hw *hw, unsigned long, 132 unsigned long); 133 void (*init)(struct clk_hw *hw); 134}; 135 136/** 137 * struct clk_init_data - holds init data that's common to all clocks and is 138 * shared between the clock provider and the common clock framework. 139 * 140 * @name: clock name 141 * @ops: operations this clock supports 142 * @parent_names: array of string names for all possible parents 143 * @num_parents: number of possible parents 144 * @flags: framework-level hints and quirks 145 */ 146struct clk_init_data { 147 const char *name; 148 const struct clk_ops *ops; 149 const char **parent_names; 150 u8 num_parents; 151 unsigned long flags; 152}; 153 154/** 155 * struct clk_hw - handle for traversing from a struct clk to its corresponding 156 * hardware-specific structure. struct clk_hw should be declared within struct 157 * clk_foo and then referenced by the struct clk instance that uses struct 158 * clk_foo's clk_ops 159 * 160 * @clk: pointer to the struct clk instance that points back to this struct 161 * clk_hw instance 162 * 163 * @init: pointer to struct clk_init_data that contains the init data shared 164 * with the common clock framework. 165 */ 166struct clk_hw { 167 struct clk *clk; 168 const struct clk_init_data *init; 169}; 170 171/* 172 * DOC: Basic clock implementations common to many platforms 173 * 174 * Each basic clock hardware type is comprised of a structure describing the 175 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 176 * unique flags for that hardware type, a registration function and an 177 * alternative macro for static initialization 178 */ 179 180/** 181 * struct clk_fixed_rate - fixed-rate clock 182 * @hw: handle between common and hardware-specific interfaces 183 * @fixed_rate: constant frequency of clock 184 */ 185struct clk_fixed_rate { 186 struct clk_hw hw; 187 unsigned long fixed_rate; 188 u8 flags; 189}; 190 191extern const struct clk_ops clk_fixed_rate_ops; 192struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 193 const char *parent_name, unsigned long flags, 194 unsigned long fixed_rate); 195 196void of_fixed_clk_setup(struct device_node *np); 197 198/** 199 * struct clk_gate - gating clock 200 * 201 * @hw: handle between common and hardware-specific interfaces 202 * @reg: register controlling gate 203 * @bit_idx: single bit controlling gate 204 * @flags: hardware-specific flags 205 * @lock: register lock 206 * 207 * Clock which can gate its output. Implements .enable & .disable 208 * 209 * Flags: 210 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 211 * enable the clock. Setting this flag does the opposite: setting the bit 212 * disable the clock and clearing it enables the clock 213 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 214 * of this register, and mask of gate bits are in higher 16-bit of this 215 * register. While setting the gate bits, higher 16-bit should also be 216 * updated to indicate changing gate bits. 217 */ 218struct clk_gate { 219 struct clk_hw hw; 220 void __iomem *reg; 221 u8 bit_idx; 222 u8 flags; 223 spinlock_t *lock; 224}; 225 226#define CLK_GATE_SET_TO_DISABLE BIT(0) 227#define CLK_GATE_HIWORD_MASK BIT(1) 228 229extern const struct clk_ops clk_gate_ops; 230struct clk *clk_register_gate(struct device *dev, const char *name, 231 const char *parent_name, unsigned long flags, 232 void __iomem *reg, u8 bit_idx, 233 u8 clk_gate_flags, spinlock_t *lock); 234 235struct clk_div_table { 236 unsigned int val; 237 unsigned int div; 238}; 239 240/** 241 * struct clk_divider - adjustable divider clock 242 * 243 * @hw: handle between common and hardware-specific interfaces 244 * @reg: register containing the divider 245 * @shift: shift to the divider bit field 246 * @width: width of the divider bit field 247 * @table: array of value/divider pairs, last entry should have div = 0 248 * @lock: register lock 249 * 250 * Clock with an adjustable divider affecting its output frequency. Implements 251 * .recalc_rate, .set_rate and .round_rate 252 * 253 * Flags: 254 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 255 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 256 * the raw value read from the register, with the value of zero considered 257 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 258 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 259 * the hardware register 260 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 261 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 262 * Some hardware implementations gracefully handle this case and allow a 263 * zero divisor by not modifying their input clock 264 * (divide by one / bypass). 265 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 266 * of this register, and mask of divider bits are in higher 16-bit of this 267 * register. While setting the divider bits, higher 16-bit should also be 268 * updated to indicate changing divider bits. 269 */ 270struct clk_divider { 271 struct clk_hw hw; 272 void __iomem *reg; 273 u8 shift; 274 u8 width; 275 u8 flags; 276 const struct clk_div_table *table; 277 spinlock_t *lock; 278}; 279 280#define CLK_DIVIDER_ONE_BASED BIT(0) 281#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 282#define CLK_DIVIDER_ALLOW_ZERO BIT(2) 283#define CLK_DIVIDER_HIWORD_MASK BIT(3) 284 285extern const struct clk_ops clk_divider_ops; 286struct clk *clk_register_divider(struct device *dev, const char *name, 287 const char *parent_name, unsigned long flags, 288 void __iomem *reg, u8 shift, u8 width, 289 u8 clk_divider_flags, spinlock_t *lock); 290struct clk *clk_register_divider_table(struct device *dev, const char *name, 291 const char *parent_name, unsigned long flags, 292 void __iomem *reg, u8 shift, u8 width, 293 u8 clk_divider_flags, const struct clk_div_table *table, 294 spinlock_t *lock); 295 296/** 297 * struct clk_mux - multiplexer clock 298 * 299 * @hw: handle between common and hardware-specific interfaces 300 * @reg: register controlling multiplexer 301 * @shift: shift to multiplexer bit field 302 * @width: width of mutliplexer bit field 303 * @flags: hardware-specific flags 304 * @lock: register lock 305 * 306 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 307 * and .recalc_rate 308 * 309 * Flags: 310 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 311 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 312 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 313 * register, and mask of mux bits are in higher 16-bit of this register. 314 * While setting the mux bits, higher 16-bit should also be updated to 315 * indicate changing mux bits. 316 */ 317struct clk_mux { 318 struct clk_hw hw; 319 void __iomem *reg; 320 u32 *table; 321 u32 mask; 322 u8 shift; 323 u8 flags; 324 spinlock_t *lock; 325}; 326 327#define CLK_MUX_INDEX_ONE BIT(0) 328#define CLK_MUX_INDEX_BIT BIT(1) 329#define CLK_MUX_HIWORD_MASK BIT(2) 330 331extern const struct clk_ops clk_mux_ops; 332 333struct clk *clk_register_mux(struct device *dev, const char *name, 334 const char **parent_names, u8 num_parents, unsigned long flags, 335 void __iomem *reg, u8 shift, u8 width, 336 u8 clk_mux_flags, spinlock_t *lock); 337 338struct clk *clk_register_mux_table(struct device *dev, const char *name, 339 const char **parent_names, u8 num_parents, unsigned long flags, 340 void __iomem *reg, u8 shift, u32 mask, 341 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 342 343void of_fixed_factor_clk_setup(struct device_node *node); 344 345/** 346 * struct clk_fixed_factor - fixed multiplier and divider clock 347 * 348 * @hw: handle between common and hardware-specific interfaces 349 * @mult: multiplier 350 * @div: divider 351 * 352 * Clock with a fixed multiplier and divider. The output frequency is the 353 * parent clock rate divided by div and multiplied by mult. 354 * Implements .recalc_rate, .set_rate and .round_rate 355 */ 356 357struct clk_fixed_factor { 358 struct clk_hw hw; 359 unsigned int mult; 360 unsigned int div; 361}; 362 363extern struct clk_ops clk_fixed_factor_ops; 364struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 365 const char *parent_name, unsigned long flags, 366 unsigned int mult, unsigned int div); 367 368/*** 369 * struct clk_composite - aggregate clock of mux, divider and gate clocks 370 * 371 * @hw: handle between common and hardware-specific interfaces 372 * @mux_hw: handle between composite and hardware-specific mux clock 373 * @rate_hw: handle between composite and hardware-specific rate clock 374 * @gate_hw: handle between composite and hardware-specific gate clock 375 * @mux_ops: clock ops for mux 376 * @rate_ops: clock ops for rate 377 * @gate_ops: clock ops for gate 378 */ 379struct clk_composite { 380 struct clk_hw hw; 381 struct clk_ops ops; 382 383 struct clk_hw *mux_hw; 384 struct clk_hw *rate_hw; 385 struct clk_hw *gate_hw; 386 387 const struct clk_ops *mux_ops; 388 const struct clk_ops *rate_ops; 389 const struct clk_ops *gate_ops; 390}; 391 392struct clk *clk_register_composite(struct device *dev, const char *name, 393 const char **parent_names, int num_parents, 394 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 395 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 396 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 397 unsigned long flags); 398 399/** 400 * clk_register - allocate a new clock, register it and return an opaque cookie 401 * @dev: device that is registering this clock 402 * @hw: link to hardware-specific clock data 403 * 404 * clk_register is the primary interface for populating the clock tree with new 405 * clock nodes. It returns a pointer to the newly allocated struct clk which 406 * cannot be dereferenced by driver code but may be used in conjuction with the 407 * rest of the clock API. In the event of an error clk_register will return an 408 * error code; drivers must test for an error code after calling clk_register. 409 */ 410struct clk *clk_register(struct device *dev, struct clk_hw *hw); 411struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 412 413void clk_unregister(struct clk *clk); 414void devm_clk_unregister(struct device *dev, struct clk *clk); 415 416/* helper functions */ 417const char *__clk_get_name(struct clk *clk); 418struct clk_hw *__clk_get_hw(struct clk *clk); 419u8 __clk_get_num_parents(struct clk *clk); 420struct clk *__clk_get_parent(struct clk *clk); 421unsigned int __clk_get_enable_count(struct clk *clk); 422unsigned int __clk_get_prepare_count(struct clk *clk); 423unsigned long __clk_get_rate(struct clk *clk); 424unsigned long __clk_get_flags(struct clk *clk); 425bool __clk_is_prepared(struct clk *clk); 426bool __clk_is_enabled(struct clk *clk); 427struct clk *__clk_lookup(const char *name); 428 429/* 430 * FIXME clock api without lock protection 431 */ 432int __clk_prepare(struct clk *clk); 433void __clk_unprepare(struct clk *clk); 434void __clk_reparent(struct clk *clk, struct clk *new_parent); 435unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 436 437struct of_device_id; 438 439typedef void (*of_clk_init_cb_t)(struct device_node *); 440 441struct clk_onecell_data { 442 struct clk **clks; 443 unsigned int clk_num; 444}; 445 446#define CLK_OF_DECLARE(name, compat, fn) \ 447 static const struct of_device_id __clk_of_table_##name \ 448 __used __section(__clk_of_table) \ 449 = { .compatible = compat, .data = fn }; 450 451#ifdef CONFIG_OF 452int of_clk_add_provider(struct device_node *np, 453 struct clk *(*clk_src_get)(struct of_phandle_args *args, 454 void *data), 455 void *data); 456void of_clk_del_provider(struct device_node *np); 457struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 458 void *data); 459struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 460const char *of_clk_get_parent_name(struct device_node *np, int index); 461 462void of_clk_init(const struct of_device_id *matches); 463 464#else /* !CONFIG_OF */ 465 466static inline int of_clk_add_provider(struct device_node *np, 467 struct clk *(*clk_src_get)(struct of_phandle_args *args, 468 void *data), 469 void *data) 470{ 471 return 0; 472} 473#define of_clk_del_provider(np) \ 474 { while (0); } 475static inline struct clk *of_clk_src_simple_get( 476 struct of_phandle_args *clkspec, void *data) 477{ 478 return ERR_PTR(-ENOENT); 479} 480static inline struct clk *of_clk_src_onecell_get( 481 struct of_phandle_args *clkspec, void *data) 482{ 483 return ERR_PTR(-ENOENT); 484} 485static inline const char *of_clk_get_parent_name(struct device_node *np, 486 int index) 487{ 488 return NULL; 489} 490#define of_clk_init(matches) \ 491 { while (0); } 492#endif /* CONFIG_OF */ 493#endif /* CONFIG_COMMON_CLK */ 494#endif /* CLK_PROVIDER_H */ 495