clk-provider.h revision 119c71276b43e3daf5e7b0661dcf63f224e2fc8d
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15 16#ifdef CONFIG_COMMON_CLK 17 18/* 19 * flags used across common struct clk. these flags should only affect the 20 * top-level framework. custom flags for dealing with hardware specifics 21 * belong in struct clk_foo 22 */ 23#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 24#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 25#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 26#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 28#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 29#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 30 31struct clk_hw; 32 33/** 34 * struct clk_ops - Callback operations for hardware clocks; these are to 35 * be provided by the clock implementation, and will be called by drivers 36 * through the clk_* api. 37 * 38 * @prepare: Prepare the clock for enabling. This must not return until 39 * the clock is fully prepared, and it's safe to call clk_enable. 40 * This callback is intended to allow clock implementations to 41 * do any initialisation that may sleep. Called with 42 * prepare_lock held. 43 * 44 * @unprepare: Release the clock from its prepared state. This will typically 45 * undo any work done in the @prepare callback. Called with 46 * prepare_lock held. 47 * 48 * @enable: Enable the clock atomically. This must not return until the 49 * clock is generating a valid clock signal, usable by consumer 50 * devices. Called with enable_lock held. This function must not 51 * sleep. 52 * 53 * @disable: Disable the clock atomically. Called with enable_lock held. 54 * This function must not sleep. 55 * 56 * @is_enabled: Queries the hardware to determine if the clock is enabled. 57 * This function must not sleep. Optional, if this op is not 58 * set then the enable count will be used. 59 * 60 * @recalc_rate Recalculate the rate of this clock, by quering hardware. The 61 * parent rate is an input parameter. It is up to the caller to 62 * insure that the prepare_mutex is held across this call. 63 * Returns the calculated rate. Optional, but recommended - if 64 * this op is not set then clock rate will be initialized to 0. 65 * 66 * @round_rate: Given a target rate as input, returns the closest rate actually 67 * supported by the clock. 68 * 69 * @get_parent: Queries the hardware to determine the parent of a clock. The 70 * return value is a u8 which specifies the index corresponding to 71 * the parent clock. This index can be applied to either the 72 * .parent_names or .parents arrays. In short, this function 73 * translates the parent value read from hardware into an array 74 * index. Currently only called when the clock is initialized by 75 * __clk_init. This callback is mandatory for clocks with 76 * multiple parents. It is optional (and unnecessary) for clocks 77 * with 0 or 1 parents. 78 * 79 * @set_parent: Change the input source of this clock; for clocks with multiple 80 * possible parents specify a new parent by passing in the index 81 * as a u8 corresponding to the parent in either the .parent_names 82 * or .parents arrays. This function in affect translates an 83 * array index into the value programmed into the hardware. 84 * Returns 0 on success, -EERROR otherwise. 85 * 86 * @set_rate: Change the rate of this clock. The requested rate is specified 87 * by the second argument, which should typically be the return 88 * of .round_rate call. The third argument gives the parent rate 89 * which is likely helpful for most .set_rate implementation. 90 * Returns 0 on success, -EERROR otherwise. 91 * 92 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 93 * implementations to split any work between atomic (enable) and sleepable 94 * (prepare) contexts. If enabling a clock requires code that might sleep, 95 * this must be done in clk_prepare. Clock enable code that will never be 96 * called in a sleepable context may be implement in clk_enable. 97 * 98 * Typically, drivers will call clk_prepare when a clock may be needed later 99 * (eg. when a device is opened), and clk_enable when the clock is actually 100 * required (eg. from an interrupt). Note that clk_prepare MUST have been 101 * called before clk_enable. 102 */ 103struct clk_ops { 104 int (*prepare)(struct clk_hw *hw); 105 void (*unprepare)(struct clk_hw *hw); 106 int (*enable)(struct clk_hw *hw); 107 void (*disable)(struct clk_hw *hw); 108 int (*is_enabled)(struct clk_hw *hw); 109 unsigned long (*recalc_rate)(struct clk_hw *hw, 110 unsigned long parent_rate); 111 long (*round_rate)(struct clk_hw *hw, unsigned long, 112 unsigned long *); 113 int (*set_parent)(struct clk_hw *hw, u8 index); 114 u8 (*get_parent)(struct clk_hw *hw); 115 int (*set_rate)(struct clk_hw *hw, unsigned long, 116 unsigned long); 117 void (*init)(struct clk_hw *hw); 118}; 119 120/** 121 * struct clk_init_data - holds init data that's common to all clocks and is 122 * shared between the clock provider and the common clock framework. 123 * 124 * @name: clock name 125 * @ops: operations this clock supports 126 * @parent_names: array of string names for all possible parents 127 * @num_parents: number of possible parents 128 * @flags: framework-level hints and quirks 129 */ 130struct clk_init_data { 131 const char *name; 132 const struct clk_ops *ops; 133 const char **parent_names; 134 u8 num_parents; 135 unsigned long flags; 136}; 137 138/** 139 * struct clk_hw - handle for traversing from a struct clk to its corresponding 140 * hardware-specific structure. struct clk_hw should be declared within struct 141 * clk_foo and then referenced by the struct clk instance that uses struct 142 * clk_foo's clk_ops 143 * 144 * @clk: pointer to the struct clk instance that points back to this struct 145 * clk_hw instance 146 * 147 * @init: pointer to struct clk_init_data that contains the init data shared 148 * with the common clock framework. 149 */ 150struct clk_hw { 151 struct clk *clk; 152 const struct clk_init_data *init; 153}; 154 155/* 156 * DOC: Basic clock implementations common to many platforms 157 * 158 * Each basic clock hardware type is comprised of a structure describing the 159 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 160 * unique flags for that hardware type, a registration function and an 161 * alternative macro for static initialization 162 */ 163 164/** 165 * struct clk_fixed_rate - fixed-rate clock 166 * @hw: handle between common and hardware-specific interfaces 167 * @fixed_rate: constant frequency of clock 168 */ 169struct clk_fixed_rate { 170 struct clk_hw hw; 171 unsigned long fixed_rate; 172 u8 flags; 173}; 174 175extern const struct clk_ops clk_fixed_rate_ops; 176struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 177 const char *parent_name, unsigned long flags, 178 unsigned long fixed_rate); 179 180void of_fixed_clk_setup(struct device_node *np); 181 182/** 183 * struct clk_gate - gating clock 184 * 185 * @hw: handle between common and hardware-specific interfaces 186 * @reg: register controlling gate 187 * @bit_idx: single bit controlling gate 188 * @flags: hardware-specific flags 189 * @lock: register lock 190 * 191 * Clock which can gate its output. Implements .enable & .disable 192 * 193 * Flags: 194 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 195 * enable the clock. Setting this flag does the opposite: setting the bit 196 * disable the clock and clearing it enables the clock 197 */ 198struct clk_gate { 199 struct clk_hw hw; 200 void __iomem *reg; 201 u8 bit_idx; 202 u8 flags; 203 spinlock_t *lock; 204}; 205 206#define CLK_GATE_SET_TO_DISABLE BIT(0) 207 208extern const struct clk_ops clk_gate_ops; 209struct clk *clk_register_gate(struct device *dev, const char *name, 210 const char *parent_name, unsigned long flags, 211 void __iomem *reg, u8 bit_idx, 212 u8 clk_gate_flags, spinlock_t *lock); 213 214struct clk_div_table { 215 unsigned int val; 216 unsigned int div; 217}; 218 219/** 220 * struct clk_divider - adjustable divider clock 221 * 222 * @hw: handle between common and hardware-specific interfaces 223 * @reg: register containing the divider 224 * @shift: shift to the divider bit field 225 * @width: width of the divider bit field 226 * @table: array of value/divider pairs, last entry should have div = 0 227 * @lock: register lock 228 * 229 * Clock with an adjustable divider affecting its output frequency. Implements 230 * .recalc_rate, .set_rate and .round_rate 231 * 232 * Flags: 233 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 234 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 235 * the raw value read from the register, with the value of zero considered 236 * invalid 237 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 238 * the hardware register 239 */ 240struct clk_divider { 241 struct clk_hw hw; 242 void __iomem *reg; 243 u8 shift; 244 u8 width; 245 u8 flags; 246 const struct clk_div_table *table; 247 spinlock_t *lock; 248}; 249 250#define CLK_DIVIDER_ONE_BASED BIT(0) 251#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 252 253extern const struct clk_ops clk_divider_ops; 254struct clk *clk_register_divider(struct device *dev, const char *name, 255 const char *parent_name, unsigned long flags, 256 void __iomem *reg, u8 shift, u8 width, 257 u8 clk_divider_flags, spinlock_t *lock); 258struct clk *clk_register_divider_table(struct device *dev, const char *name, 259 const char *parent_name, unsigned long flags, 260 void __iomem *reg, u8 shift, u8 width, 261 u8 clk_divider_flags, const struct clk_div_table *table, 262 spinlock_t *lock); 263 264/** 265 * struct clk_mux - multiplexer clock 266 * 267 * @hw: handle between common and hardware-specific interfaces 268 * @reg: register controlling multiplexer 269 * @shift: shift to multiplexer bit field 270 * @width: width of mutliplexer bit field 271 * @num_clks: number of parent clocks 272 * @lock: register lock 273 * 274 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 275 * and .recalc_rate 276 * 277 * Flags: 278 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 279 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 280 */ 281struct clk_mux { 282 struct clk_hw hw; 283 void __iomem *reg; 284 u8 shift; 285 u8 width; 286 u8 flags; 287 spinlock_t *lock; 288}; 289 290#define CLK_MUX_INDEX_ONE BIT(0) 291#define CLK_MUX_INDEX_BIT BIT(1) 292 293extern const struct clk_ops clk_mux_ops; 294struct clk *clk_register_mux(struct device *dev, const char *name, 295 const char **parent_names, u8 num_parents, unsigned long flags, 296 void __iomem *reg, u8 shift, u8 width, 297 u8 clk_mux_flags, spinlock_t *lock); 298 299/** 300 * struct clk_fixed_factor - fixed multiplier and divider clock 301 * 302 * @hw: handle between common and hardware-specific interfaces 303 * @mult: multiplier 304 * @div: divider 305 * 306 * Clock with a fixed multiplier and divider. The output frequency is the 307 * parent clock rate divided by div and multiplied by mult. 308 * Implements .recalc_rate, .set_rate and .round_rate 309 */ 310 311struct clk_fixed_factor { 312 struct clk_hw hw; 313 unsigned int mult; 314 unsigned int div; 315}; 316 317extern struct clk_ops clk_fixed_factor_ops; 318struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 319 const char *parent_name, unsigned long flags, 320 unsigned int mult, unsigned int div); 321 322/** 323 * clk_register - allocate a new clock, register it and return an opaque cookie 324 * @dev: device that is registering this clock 325 * @hw: link to hardware-specific clock data 326 * 327 * clk_register is the primary interface for populating the clock tree with new 328 * clock nodes. It returns a pointer to the newly allocated struct clk which 329 * cannot be dereferenced by driver code but may be used in conjuction with the 330 * rest of the clock API. In the event of an error clk_register will return an 331 * error code; drivers must test for an error code after calling clk_register. 332 */ 333struct clk *clk_register(struct device *dev, struct clk_hw *hw); 334 335void clk_unregister(struct clk *clk); 336 337/* helper functions */ 338const char *__clk_get_name(struct clk *clk); 339struct clk_hw *__clk_get_hw(struct clk *clk); 340u8 __clk_get_num_parents(struct clk *clk); 341struct clk *__clk_get_parent(struct clk *clk); 342inline int __clk_get_enable_count(struct clk *clk); 343inline int __clk_get_prepare_count(struct clk *clk); 344unsigned long __clk_get_rate(struct clk *clk); 345unsigned long __clk_get_flags(struct clk *clk); 346int __clk_is_enabled(struct clk *clk); 347struct clk *__clk_lookup(const char *name); 348 349/* 350 * FIXME clock api without lock protection 351 */ 352int __clk_prepare(struct clk *clk); 353void __clk_unprepare(struct clk *clk); 354void __clk_reparent(struct clk *clk, struct clk *new_parent); 355unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 356 357struct of_device_id; 358 359typedef void (*of_clk_init_cb_t)(struct device_node *); 360 361int of_clk_add_provider(struct device_node *np, 362 struct clk *(*clk_src_get)(struct of_phandle_args *args, 363 void *data), 364 void *data); 365void of_clk_del_provider(struct device_node *np); 366struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 367 void *data); 368struct clk_onecell_data { 369 struct clk **clks; 370 unsigned int clk_num; 371}; 372struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 373const char *of_clk_get_parent_name(struct device_node *np, int index); 374void of_clk_init(const struct of_device_id *matches); 375 376#endif /* CONFIG_COMMON_CLK */ 377#endif /* CLK_PROVIDER_H */ 378