clk-provider.h revision 355bb165cd8bad2500df37437a9121f0177b6741
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15#include <linux/io.h> 16#include <linux/of.h> 17 18#ifdef CONFIG_COMMON_CLK 19 20/* 21 * flags used across common struct clk. these flags should only affect the 22 * top-level framework. custom flags for dealing with hardware specifics 23 * belong in struct clk_foo 24 */ 25#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 26#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 27#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 28#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 29#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 30#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 31#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 32#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 33#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 34 35struct clk_hw; 36struct dentry; 37 38/** 39 * struct clk_ops - Callback operations for hardware clocks; these are to 40 * be provided by the clock implementation, and will be called by drivers 41 * through the clk_* api. 42 * 43 * @prepare: Prepare the clock for enabling. This must not return until 44 * the clock is fully prepared, and it's safe to call clk_enable. 45 * This callback is intended to allow clock implementations to 46 * do any initialisation that may sleep. Called with 47 * prepare_lock held. 48 * 49 * @unprepare: Release the clock from its prepared state. This will typically 50 * undo any work done in the @prepare callback. Called with 51 * prepare_lock held. 52 * 53 * @is_prepared: Queries the hardware to determine if the clock is prepared. 54 * This function is allowed to sleep. Optional, if this op is not 55 * set then the prepare count will be used. 56 * 57 * @unprepare_unused: Unprepare the clock atomically. Only called from 58 * clk_disable_unused for prepare clocks with special needs. 59 * Called with prepare mutex held. This function may sleep. 60 * 61 * @enable: Enable the clock atomically. This must not return until the 62 * clock is generating a valid clock signal, usable by consumer 63 * devices. Called with enable_lock held. This function must not 64 * sleep. 65 * 66 * @disable: Disable the clock atomically. Called with enable_lock held. 67 * This function must not sleep. 68 * 69 * @is_enabled: Queries the hardware to determine if the clock is enabled. 70 * This function must not sleep. Optional, if this op is not 71 * set then the enable count will be used. 72 * 73 * @disable_unused: Disable the clock atomically. Only called from 74 * clk_disable_unused for gate clocks with special needs. 75 * Called with enable_lock held. This function must not 76 * sleep. 77 * 78 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 79 * parent rate is an input parameter. It is up to the caller to 80 * ensure that the prepare_mutex is held across this call. 81 * Returns the calculated rate. Optional, but recommended - if 82 * this op is not set then clock rate will be initialized to 0. 83 * 84 * @round_rate: Given a target rate as input, returns the closest rate actually 85 * supported by the clock. The parent rate is an input/output 86 * parameter. 87 * 88 * @determine_rate: Given a target rate as input, returns the closest rate 89 * actually supported by the clock, and optionally the parent clock 90 * that should be used to provide the clock rate. 91 * 92 * @set_parent: Change the input source of this clock; for clocks with multiple 93 * possible parents specify a new parent by passing in the index 94 * as a u8 corresponding to the parent in either the .parent_names 95 * or .parents arrays. This function in affect translates an 96 * array index into the value programmed into the hardware. 97 * Returns 0 on success, -EERROR otherwise. 98 * 99 * @get_parent: Queries the hardware to determine the parent of a clock. The 100 * return value is a u8 which specifies the index corresponding to 101 * the parent clock. This index can be applied to either the 102 * .parent_names or .parents arrays. In short, this function 103 * translates the parent value read from hardware into an array 104 * index. Currently only called when the clock is initialized by 105 * __clk_init. This callback is mandatory for clocks with 106 * multiple parents. It is optional (and unnecessary) for clocks 107 * with 0 or 1 parents. 108 * 109 * @set_rate: Change the rate of this clock. The requested rate is specified 110 * by the second argument, which should typically be the return 111 * of .round_rate call. The third argument gives the parent rate 112 * which is likely helpful for most .set_rate implementation. 113 * Returns 0 on success, -EERROR otherwise. 114 * 115 * @set_rate_and_parent: Change the rate and the parent of this clock. The 116 * requested rate is specified by the second argument, which 117 * should typically be the return of .round_rate call. The 118 * third argument gives the parent rate which is likely helpful 119 * for most .set_rate_and_parent implementation. The fourth 120 * argument gives the parent index. This callback is optional (and 121 * unnecessary) for clocks with 0 or 1 parents as well as 122 * for clocks that can tolerate switching the rate and the parent 123 * separately via calls to .set_parent and .set_rate. 124 * Returns 0 on success, -EERROR otherwise. 125 * 126 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 127 * is expressed in ppb (parts per billion). The parent accuracy is 128 * an input parameter. 129 * Returns the calculated accuracy. Optional - if this op is not 130 * set then clock accuracy will be initialized to parent accuracy 131 * or 0 (perfect clock) if clock has no parent. 132 * 133 * @set_phase: Shift the phase this clock signal in degrees specified 134 * by the second argument. Valid values for degrees are 135 * 0-359. Return 0 on success, otherwise -EERROR. 136 * 137 * @init: Perform platform-specific initialization magic. 138 * This is not not used by any of the basic clock types. 139 * Please consider other ways of solving initialization problems 140 * before using this callback, as its use is discouraged. 141 * 142 * @debug_init: Set up type-specific debugfs entries for this clock. This 143 * is called once, after the debugfs directory entry for this 144 * clock has been created. The dentry pointer representing that 145 * directory is provided as an argument. Called with 146 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 147 * 148 * 149 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 150 * implementations to split any work between atomic (enable) and sleepable 151 * (prepare) contexts. If enabling a clock requires code that might sleep, 152 * this must be done in clk_prepare. Clock enable code that will never be 153 * called in a sleepable context may be implemented in clk_enable. 154 * 155 * Typically, drivers will call clk_prepare when a clock may be needed later 156 * (eg. when a device is opened), and clk_enable when the clock is actually 157 * required (eg. from an interrupt). Note that clk_prepare MUST have been 158 * called before clk_enable. 159 */ 160struct clk_ops { 161 int (*prepare)(struct clk_hw *hw); 162 void (*unprepare)(struct clk_hw *hw); 163 int (*is_prepared)(struct clk_hw *hw); 164 void (*unprepare_unused)(struct clk_hw *hw); 165 int (*enable)(struct clk_hw *hw); 166 void (*disable)(struct clk_hw *hw); 167 int (*is_enabled)(struct clk_hw *hw); 168 void (*disable_unused)(struct clk_hw *hw); 169 unsigned long (*recalc_rate)(struct clk_hw *hw, 170 unsigned long parent_rate); 171 long (*round_rate)(struct clk_hw *hw, unsigned long rate, 172 unsigned long *parent_rate); 173 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 174 unsigned long *best_parent_rate, 175 struct clk **best_parent_clk); 176 int (*set_parent)(struct clk_hw *hw, u8 index); 177 u8 (*get_parent)(struct clk_hw *hw); 178 int (*set_rate)(struct clk_hw *hw, unsigned long rate, 179 unsigned long parent_rate); 180 int (*set_rate_and_parent)(struct clk_hw *hw, 181 unsigned long rate, 182 unsigned long parent_rate, u8 index); 183 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 184 unsigned long parent_accuracy); 185 int (*set_phase)(struct clk_hw *hw, int degrees); 186 void (*init)(struct clk_hw *hw); 187 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 188}; 189 190/** 191 * struct clk_init_data - holds init data that's common to all clocks and is 192 * shared between the clock provider and the common clock framework. 193 * 194 * @name: clock name 195 * @ops: operations this clock supports 196 * @parent_names: array of string names for all possible parents 197 * @num_parents: number of possible parents 198 * @flags: framework-level hints and quirks 199 */ 200struct clk_init_data { 201 const char *name; 202 const struct clk_ops *ops; 203 const char **parent_names; 204 u8 num_parents; 205 unsigned long flags; 206}; 207 208/** 209 * struct clk_hw - handle for traversing from a struct clk to its corresponding 210 * hardware-specific structure. struct clk_hw should be declared within struct 211 * clk_foo and then referenced by the struct clk instance that uses struct 212 * clk_foo's clk_ops 213 * 214 * @clk: pointer to the struct clk instance that points back to this struct 215 * clk_hw instance 216 * 217 * @init: pointer to struct clk_init_data that contains the init data shared 218 * with the common clock framework. 219 */ 220struct clk_hw { 221 struct clk *clk; 222 const struct clk_init_data *init; 223}; 224 225/* 226 * DOC: Basic clock implementations common to many platforms 227 * 228 * Each basic clock hardware type is comprised of a structure describing the 229 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 230 * unique flags for that hardware type, a registration function and an 231 * alternative macro for static initialization 232 */ 233 234/** 235 * struct clk_fixed_rate - fixed-rate clock 236 * @hw: handle between common and hardware-specific interfaces 237 * @fixed_rate: constant frequency of clock 238 */ 239struct clk_fixed_rate { 240 struct clk_hw hw; 241 unsigned long fixed_rate; 242 unsigned long fixed_accuracy; 243 u8 flags; 244}; 245 246extern const struct clk_ops clk_fixed_rate_ops; 247struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 248 const char *parent_name, unsigned long flags, 249 unsigned long fixed_rate); 250struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 251 const char *name, const char *parent_name, unsigned long flags, 252 unsigned long fixed_rate, unsigned long fixed_accuracy); 253 254void of_fixed_clk_setup(struct device_node *np); 255 256/** 257 * struct clk_gate - gating clock 258 * 259 * @hw: handle between common and hardware-specific interfaces 260 * @reg: register controlling gate 261 * @bit_idx: single bit controlling gate 262 * @flags: hardware-specific flags 263 * @lock: register lock 264 * 265 * Clock which can gate its output. Implements .enable & .disable 266 * 267 * Flags: 268 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 269 * enable the clock. Setting this flag does the opposite: setting the bit 270 * disable the clock and clearing it enables the clock 271 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 272 * of this register, and mask of gate bits are in higher 16-bit of this 273 * register. While setting the gate bits, higher 16-bit should also be 274 * updated to indicate changing gate bits. 275 */ 276struct clk_gate { 277 struct clk_hw hw; 278 void __iomem *reg; 279 u8 bit_idx; 280 u8 flags; 281 spinlock_t *lock; 282}; 283 284#define CLK_GATE_SET_TO_DISABLE BIT(0) 285#define CLK_GATE_HIWORD_MASK BIT(1) 286 287extern const struct clk_ops clk_gate_ops; 288struct clk *clk_register_gate(struct device *dev, const char *name, 289 const char *parent_name, unsigned long flags, 290 void __iomem *reg, u8 bit_idx, 291 u8 clk_gate_flags, spinlock_t *lock); 292 293struct clk_div_table { 294 unsigned int val; 295 unsigned int div; 296}; 297 298/** 299 * struct clk_divider - adjustable divider clock 300 * 301 * @hw: handle between common and hardware-specific interfaces 302 * @reg: register containing the divider 303 * @shift: shift to the divider bit field 304 * @width: width of the divider bit field 305 * @table: array of value/divider pairs, last entry should have div = 0 306 * @lock: register lock 307 * 308 * Clock with an adjustable divider affecting its output frequency. Implements 309 * .recalc_rate, .set_rate and .round_rate 310 * 311 * Flags: 312 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 313 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 314 * the raw value read from the register, with the value of zero considered 315 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 316 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 317 * the hardware register 318 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 319 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 320 * Some hardware implementations gracefully handle this case and allow a 321 * zero divisor by not modifying their input clock 322 * (divide by one / bypass). 323 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 324 * of this register, and mask of divider bits are in higher 16-bit of this 325 * register. While setting the divider bits, higher 16-bit should also be 326 * updated to indicate changing divider bits. 327 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded 328 * to the closest integer instead of the up one. 329 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should 330 * not be changed by the clock framework. 331 */ 332struct clk_divider { 333 struct clk_hw hw; 334 void __iomem *reg; 335 u8 shift; 336 u8 width; 337 u8 flags; 338 const struct clk_div_table *table; 339 spinlock_t *lock; 340}; 341 342#define CLK_DIVIDER_ONE_BASED BIT(0) 343#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 344#define CLK_DIVIDER_ALLOW_ZERO BIT(2) 345#define CLK_DIVIDER_HIWORD_MASK BIT(3) 346#define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 347#define CLK_DIVIDER_READ_ONLY BIT(5) 348 349extern const struct clk_ops clk_divider_ops; 350extern const struct clk_ops clk_divider_ro_ops; 351struct clk *clk_register_divider(struct device *dev, const char *name, 352 const char *parent_name, unsigned long flags, 353 void __iomem *reg, u8 shift, u8 width, 354 u8 clk_divider_flags, spinlock_t *lock); 355struct clk *clk_register_divider_table(struct device *dev, const char *name, 356 const char *parent_name, unsigned long flags, 357 void __iomem *reg, u8 shift, u8 width, 358 u8 clk_divider_flags, const struct clk_div_table *table, 359 spinlock_t *lock); 360 361/** 362 * struct clk_mux - multiplexer clock 363 * 364 * @hw: handle between common and hardware-specific interfaces 365 * @reg: register controlling multiplexer 366 * @shift: shift to multiplexer bit field 367 * @width: width of mutliplexer bit field 368 * @flags: hardware-specific flags 369 * @lock: register lock 370 * 371 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 372 * and .recalc_rate 373 * 374 * Flags: 375 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 376 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 377 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 378 * register, and mask of mux bits are in higher 16-bit of this register. 379 * While setting the mux bits, higher 16-bit should also be updated to 380 * indicate changing mux bits. 381 */ 382struct clk_mux { 383 struct clk_hw hw; 384 void __iomem *reg; 385 u32 *table; 386 u32 mask; 387 u8 shift; 388 u8 flags; 389 spinlock_t *lock; 390}; 391 392#define CLK_MUX_INDEX_ONE BIT(0) 393#define CLK_MUX_INDEX_BIT BIT(1) 394#define CLK_MUX_HIWORD_MASK BIT(2) 395#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 396 397extern const struct clk_ops clk_mux_ops; 398extern const struct clk_ops clk_mux_ro_ops; 399 400struct clk *clk_register_mux(struct device *dev, const char *name, 401 const char **parent_names, u8 num_parents, unsigned long flags, 402 void __iomem *reg, u8 shift, u8 width, 403 u8 clk_mux_flags, spinlock_t *lock); 404 405struct clk *clk_register_mux_table(struct device *dev, const char *name, 406 const char **parent_names, u8 num_parents, unsigned long flags, 407 void __iomem *reg, u8 shift, u32 mask, 408 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 409 410void of_fixed_factor_clk_setup(struct device_node *node); 411 412/** 413 * struct clk_fixed_factor - fixed multiplier and divider clock 414 * 415 * @hw: handle between common and hardware-specific interfaces 416 * @mult: multiplier 417 * @div: divider 418 * 419 * Clock with a fixed multiplier and divider. The output frequency is the 420 * parent clock rate divided by div and multiplied by mult. 421 * Implements .recalc_rate, .set_rate and .round_rate 422 */ 423 424struct clk_fixed_factor { 425 struct clk_hw hw; 426 unsigned int mult; 427 unsigned int div; 428}; 429 430extern struct clk_ops clk_fixed_factor_ops; 431struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 432 const char *parent_name, unsigned long flags, 433 unsigned int mult, unsigned int div); 434 435/** 436 * struct clk_fractional_divider - adjustable fractional divider clock 437 * 438 * @hw: handle between common and hardware-specific interfaces 439 * @reg: register containing the divider 440 * @mshift: shift to the numerator bit field 441 * @mwidth: width of the numerator bit field 442 * @nshift: shift to the denominator bit field 443 * @nwidth: width of the denominator bit field 444 * @lock: register lock 445 * 446 * Clock with adjustable fractional divider affecting its output frequency. 447 */ 448 449struct clk_fractional_divider { 450 struct clk_hw hw; 451 void __iomem *reg; 452 u8 mshift; 453 u32 mmask; 454 u8 nshift; 455 u32 nmask; 456 u8 flags; 457 spinlock_t *lock; 458}; 459 460extern const struct clk_ops clk_fractional_divider_ops; 461struct clk *clk_register_fractional_divider(struct device *dev, 462 const char *name, const char *parent_name, unsigned long flags, 463 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth, 464 u8 clk_divider_flags, spinlock_t *lock); 465 466/*** 467 * struct clk_composite - aggregate clock of mux, divider and gate clocks 468 * 469 * @hw: handle between common and hardware-specific interfaces 470 * @mux_hw: handle between composite and hardware-specific mux clock 471 * @rate_hw: handle between composite and hardware-specific rate clock 472 * @gate_hw: handle between composite and hardware-specific gate clock 473 * @mux_ops: clock ops for mux 474 * @rate_ops: clock ops for rate 475 * @gate_ops: clock ops for gate 476 */ 477struct clk_composite { 478 struct clk_hw hw; 479 struct clk_ops ops; 480 481 struct clk_hw *mux_hw; 482 struct clk_hw *rate_hw; 483 struct clk_hw *gate_hw; 484 485 const struct clk_ops *mux_ops; 486 const struct clk_ops *rate_ops; 487 const struct clk_ops *gate_ops; 488}; 489 490struct clk *clk_register_composite(struct device *dev, const char *name, 491 const char **parent_names, int num_parents, 492 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 493 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 494 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 495 unsigned long flags); 496 497/** 498 * clk_register - allocate a new clock, register it and return an opaque cookie 499 * @dev: device that is registering this clock 500 * @hw: link to hardware-specific clock data 501 * 502 * clk_register is the primary interface for populating the clock tree with new 503 * clock nodes. It returns a pointer to the newly allocated struct clk which 504 * cannot be dereferenced by driver code but may be used in conjuction with the 505 * rest of the clock API. In the event of an error clk_register will return an 506 * error code; drivers must test for an error code after calling clk_register. 507 */ 508struct clk *clk_register(struct device *dev, struct clk_hw *hw); 509struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 510 511void clk_unregister(struct clk *clk); 512void devm_clk_unregister(struct device *dev, struct clk *clk); 513 514/* helper functions */ 515const char *__clk_get_name(struct clk *clk); 516struct clk_hw *__clk_get_hw(struct clk *clk); 517u8 __clk_get_num_parents(struct clk *clk); 518struct clk *__clk_get_parent(struct clk *clk); 519struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); 520unsigned int __clk_get_enable_count(struct clk *clk); 521unsigned int __clk_get_prepare_count(struct clk *clk); 522unsigned long __clk_get_rate(struct clk *clk); 523unsigned long __clk_get_accuracy(struct clk *clk); 524unsigned long __clk_get_flags(struct clk *clk); 525bool __clk_is_prepared(struct clk *clk); 526bool __clk_is_enabled(struct clk *clk); 527struct clk *__clk_lookup(const char *name); 528long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 529 unsigned long *best_parent_rate, 530 struct clk **best_parent_p); 531 532/* 533 * FIXME clock api without lock protection 534 */ 535int __clk_prepare(struct clk *clk); 536void __clk_unprepare(struct clk *clk); 537void __clk_reparent(struct clk *clk, struct clk *new_parent); 538unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 539 540struct of_device_id; 541 542typedef void (*of_clk_init_cb_t)(struct device_node *); 543 544struct clk_onecell_data { 545 struct clk **clks; 546 unsigned int clk_num; 547}; 548 549extern struct of_device_id __clk_of_table; 550 551#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 552 553#ifdef CONFIG_OF 554int of_clk_add_provider(struct device_node *np, 555 struct clk *(*clk_src_get)(struct of_phandle_args *args, 556 void *data), 557 void *data); 558void of_clk_del_provider(struct device_node *np); 559struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 560 void *data); 561struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 562int of_clk_get_parent_count(struct device_node *np); 563const char *of_clk_get_parent_name(struct device_node *np, int index); 564 565void of_clk_init(const struct of_device_id *matches); 566 567#else /* !CONFIG_OF */ 568 569static inline int of_clk_add_provider(struct device_node *np, 570 struct clk *(*clk_src_get)(struct of_phandle_args *args, 571 void *data), 572 void *data) 573{ 574 return 0; 575} 576#define of_clk_del_provider(np) \ 577 { while (0); } 578static inline struct clk *of_clk_src_simple_get( 579 struct of_phandle_args *clkspec, void *data) 580{ 581 return ERR_PTR(-ENOENT); 582} 583static inline struct clk *of_clk_src_onecell_get( 584 struct of_phandle_args *clkspec, void *data) 585{ 586 return ERR_PTR(-ENOENT); 587} 588static inline const char *of_clk_get_parent_name(struct device_node *np, 589 int index) 590{ 591 return NULL; 592} 593#define of_clk_init(matches) \ 594 { while (0); } 595#endif /* CONFIG_OF */ 596 597/* 598 * wrap access to peripherals in accessor routines 599 * for improved portability across platforms 600 */ 601 602#if IS_ENABLED(CONFIG_PPC) 603 604static inline u32 clk_readl(u32 __iomem *reg) 605{ 606 return ioread32be(reg); 607} 608 609static inline void clk_writel(u32 val, u32 __iomem *reg) 610{ 611 iowrite32be(val, reg); 612} 613 614#else /* platform dependent I/O accessors */ 615 616static inline u32 clk_readl(u32 __iomem *reg) 617{ 618 return readl(reg); 619} 620 621static inline void clk_writel(u32 val, u32 __iomem *reg) 622{ 623 writel(val, reg); 624} 625 626#endif /* platform dependent I/O accessors */ 627 628#ifdef CONFIG_DEBUG_FS 629struct dentry *clk_debugfs_add_file(struct clk *clk, char *name, umode_t mode, 630 void *data, const struct file_operations *fops); 631#endif 632 633#endif /* CONFIG_COMMON_CLK */ 634#endif /* CLK_PROVIDER_H */ 635