clk-provider.h revision 3fa2252b7a78a8057017471a28f47b306e95ee26
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15#include <linux/io.h> 16 17#ifdef CONFIG_COMMON_CLK 18 19/* 20 * flags used across common struct clk. these flags should only affect the 21 * top-level framework. custom flags for dealing with hardware specifics 22 * belong in struct clk_foo 23 */ 24#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 25#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 26#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 27#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 28#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 29#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 30#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 31#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 32#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 33 34struct clk_hw; 35 36/** 37 * struct clk_ops - Callback operations for hardware clocks; these are to 38 * be provided by the clock implementation, and will be called by drivers 39 * through the clk_* api. 40 * 41 * @prepare: Prepare the clock for enabling. This must not return until 42 * the clock is fully prepared, and it's safe to call clk_enable. 43 * This callback is intended to allow clock implementations to 44 * do any initialisation that may sleep. Called with 45 * prepare_lock held. 46 * 47 * @unprepare: Release the clock from its prepared state. This will typically 48 * undo any work done in the @prepare callback. Called with 49 * prepare_lock held. 50 * 51 * @is_prepared: Queries the hardware to determine if the clock is prepared. 52 * This function is allowed to sleep. Optional, if this op is not 53 * set then the prepare count will be used. 54 * 55 * @unprepare_unused: Unprepare the clock atomically. Only called from 56 * clk_disable_unused for prepare clocks with special needs. 57 * Called with prepare mutex held. This function may sleep. 58 * 59 * @enable: Enable the clock atomically. This must not return until the 60 * clock is generating a valid clock signal, usable by consumer 61 * devices. Called with enable_lock held. This function must not 62 * sleep. 63 * 64 * @disable: Disable the clock atomically. Called with enable_lock held. 65 * This function must not sleep. 66 * 67 * @is_enabled: Queries the hardware to determine if the clock is enabled. 68 * This function must not sleep. Optional, if this op is not 69 * set then the enable count will be used. 70 * 71 * @disable_unused: Disable the clock atomically. Only called from 72 * clk_disable_unused for gate clocks with special needs. 73 * Called with enable_lock held. This function must not 74 * sleep. 75 * 76 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 77 * parent rate is an input parameter. It is up to the caller to 78 * ensure that the prepare_mutex is held across this call. 79 * Returns the calculated rate. Optional, but recommended - if 80 * this op is not set then clock rate will be initialized to 0. 81 * 82 * @round_rate: Given a target rate as input, returns the closest rate actually 83 * supported by the clock. 84 * 85 * @determine_rate: Given a target rate as input, returns the closest rate 86 * actually supported by the clock, and optionally the parent clock 87 * that should be used to provide the clock rate. 88 * 89 * @get_parent: Queries the hardware to determine the parent of a clock. The 90 * return value is a u8 which specifies the index corresponding to 91 * the parent clock. This index can be applied to either the 92 * .parent_names or .parents arrays. In short, this function 93 * translates the parent value read from hardware into an array 94 * index. Currently only called when the clock is initialized by 95 * __clk_init. This callback is mandatory for clocks with 96 * multiple parents. It is optional (and unnecessary) for clocks 97 * with 0 or 1 parents. 98 * 99 * @set_parent: Change the input source of this clock; for clocks with multiple 100 * possible parents specify a new parent by passing in the index 101 * as a u8 corresponding to the parent in either the .parent_names 102 * or .parents arrays. This function in affect translates an 103 * array index into the value programmed into the hardware. 104 * Returns 0 on success, -EERROR otherwise. 105 * 106 * @set_rate: Change the rate of this clock. The requested rate is specified 107 * by the second argument, which should typically be the return 108 * of .round_rate call. The third argument gives the parent rate 109 * which is likely helpful for most .set_rate implementation. 110 * Returns 0 on success, -EERROR otherwise. 111 * 112 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 113 * is expressed in ppb (parts per billion). The parent accuracy is 114 * an input parameter. 115 * Returns the calculated accuracy. Optional - if this op is not 116 * set then clock accuracy will be initialized to parent accuracy 117 * or 0 (perfect clock) if clock has no parent. 118 * 119 * @set_rate_and_parent: Change the rate and the parent of this clock. The 120 * requested rate is specified by the second argument, which 121 * should typically be the return of .round_rate call. The 122 * third argument gives the parent rate which is likely helpful 123 * for most .set_rate_and_parent implementation. The fourth 124 * argument gives the parent index. This callback is optional (and 125 * unnecessary) for clocks with 0 or 1 parents as well as 126 * for clocks that can tolerate switching the rate and the parent 127 * separately via calls to .set_parent and .set_rate. 128 * Returns 0 on success, -EERROR otherwise. 129 * 130 * 131 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 132 * implementations to split any work between atomic (enable) and sleepable 133 * (prepare) contexts. If enabling a clock requires code that might sleep, 134 * this must be done in clk_prepare. Clock enable code that will never be 135 * called in a sleepable context may be implemented in clk_enable. 136 * 137 * Typically, drivers will call clk_prepare when a clock may be needed later 138 * (eg. when a device is opened), and clk_enable when the clock is actually 139 * required (eg. from an interrupt). Note that clk_prepare MUST have been 140 * called before clk_enable. 141 */ 142struct clk_ops { 143 int (*prepare)(struct clk_hw *hw); 144 void (*unprepare)(struct clk_hw *hw); 145 int (*is_prepared)(struct clk_hw *hw); 146 void (*unprepare_unused)(struct clk_hw *hw); 147 int (*enable)(struct clk_hw *hw); 148 void (*disable)(struct clk_hw *hw); 149 int (*is_enabled)(struct clk_hw *hw); 150 void (*disable_unused)(struct clk_hw *hw); 151 unsigned long (*recalc_rate)(struct clk_hw *hw, 152 unsigned long parent_rate); 153 long (*round_rate)(struct clk_hw *hw, unsigned long, 154 unsigned long *); 155 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 156 unsigned long *best_parent_rate, 157 struct clk **best_parent_clk); 158 int (*set_parent)(struct clk_hw *hw, u8 index); 159 u8 (*get_parent)(struct clk_hw *hw); 160 int (*set_rate)(struct clk_hw *hw, unsigned long, 161 unsigned long); 162 int (*set_rate_and_parent)(struct clk_hw *hw, 163 unsigned long rate, 164 unsigned long parent_rate, u8 index); 165 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 166 unsigned long parent_accuracy); 167 void (*init)(struct clk_hw *hw); 168}; 169 170/** 171 * struct clk_init_data - holds init data that's common to all clocks and is 172 * shared between the clock provider and the common clock framework. 173 * 174 * @name: clock name 175 * @ops: operations this clock supports 176 * @parent_names: array of string names for all possible parents 177 * @num_parents: number of possible parents 178 * @flags: framework-level hints and quirks 179 */ 180struct clk_init_data { 181 const char *name; 182 const struct clk_ops *ops; 183 const char **parent_names; 184 u8 num_parents; 185 unsigned long flags; 186}; 187 188/** 189 * struct clk_hw - handle for traversing from a struct clk to its corresponding 190 * hardware-specific structure. struct clk_hw should be declared within struct 191 * clk_foo and then referenced by the struct clk instance that uses struct 192 * clk_foo's clk_ops 193 * 194 * @clk: pointer to the struct clk instance that points back to this struct 195 * clk_hw instance 196 * 197 * @init: pointer to struct clk_init_data that contains the init data shared 198 * with the common clock framework. 199 */ 200struct clk_hw { 201 struct clk *clk; 202 const struct clk_init_data *init; 203}; 204 205/* 206 * DOC: Basic clock implementations common to many platforms 207 * 208 * Each basic clock hardware type is comprised of a structure describing the 209 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 210 * unique flags for that hardware type, a registration function and an 211 * alternative macro for static initialization 212 */ 213 214/** 215 * struct clk_fixed_rate - fixed-rate clock 216 * @hw: handle between common and hardware-specific interfaces 217 * @fixed_rate: constant frequency of clock 218 */ 219struct clk_fixed_rate { 220 struct clk_hw hw; 221 unsigned long fixed_rate; 222 unsigned long fixed_accuracy; 223 u8 flags; 224}; 225 226extern const struct clk_ops clk_fixed_rate_ops; 227struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 228 const char *parent_name, unsigned long flags, 229 unsigned long fixed_rate); 230struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 231 const char *name, const char *parent_name, unsigned long flags, 232 unsigned long fixed_rate, unsigned long fixed_accuracy); 233 234void of_fixed_clk_setup(struct device_node *np); 235 236/** 237 * struct clk_gate - gating clock 238 * 239 * @hw: handle between common and hardware-specific interfaces 240 * @reg: register controlling gate 241 * @bit_idx: single bit controlling gate 242 * @flags: hardware-specific flags 243 * @lock: register lock 244 * 245 * Clock which can gate its output. Implements .enable & .disable 246 * 247 * Flags: 248 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 249 * enable the clock. Setting this flag does the opposite: setting the bit 250 * disable the clock and clearing it enables the clock 251 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 252 * of this register, and mask of gate bits are in higher 16-bit of this 253 * register. While setting the gate bits, higher 16-bit should also be 254 * updated to indicate changing gate bits. 255 */ 256struct clk_gate { 257 struct clk_hw hw; 258 void __iomem *reg; 259 u8 bit_idx; 260 u8 flags; 261 spinlock_t *lock; 262}; 263 264#define CLK_GATE_SET_TO_DISABLE BIT(0) 265#define CLK_GATE_HIWORD_MASK BIT(1) 266 267extern const struct clk_ops clk_gate_ops; 268struct clk *clk_register_gate(struct device *dev, const char *name, 269 const char *parent_name, unsigned long flags, 270 void __iomem *reg, u8 bit_idx, 271 u8 clk_gate_flags, spinlock_t *lock); 272 273struct clk_div_table { 274 unsigned int val; 275 unsigned int div; 276}; 277 278/** 279 * struct clk_divider - adjustable divider clock 280 * 281 * @hw: handle between common and hardware-specific interfaces 282 * @reg: register containing the divider 283 * @shift: shift to the divider bit field 284 * @width: width of the divider bit field 285 * @table: array of value/divider pairs, last entry should have div = 0 286 * @lock: register lock 287 * 288 * Clock with an adjustable divider affecting its output frequency. Implements 289 * .recalc_rate, .set_rate and .round_rate 290 * 291 * Flags: 292 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 293 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 294 * the raw value read from the register, with the value of zero considered 295 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 296 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 297 * the hardware register 298 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 299 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 300 * Some hardware implementations gracefully handle this case and allow a 301 * zero divisor by not modifying their input clock 302 * (divide by one / bypass). 303 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 304 * of this register, and mask of divider bits are in higher 16-bit of this 305 * register. While setting the divider bits, higher 16-bit should also be 306 * updated to indicate changing divider bits. 307 */ 308struct clk_divider { 309 struct clk_hw hw; 310 void __iomem *reg; 311 u8 shift; 312 u8 width; 313 u8 flags; 314 const struct clk_div_table *table; 315 spinlock_t *lock; 316}; 317 318#define CLK_DIVIDER_ONE_BASED BIT(0) 319#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 320#define CLK_DIVIDER_ALLOW_ZERO BIT(2) 321#define CLK_DIVIDER_HIWORD_MASK BIT(3) 322 323extern const struct clk_ops clk_divider_ops; 324struct clk *clk_register_divider(struct device *dev, const char *name, 325 const char *parent_name, unsigned long flags, 326 void __iomem *reg, u8 shift, u8 width, 327 u8 clk_divider_flags, spinlock_t *lock); 328struct clk *clk_register_divider_table(struct device *dev, const char *name, 329 const char *parent_name, unsigned long flags, 330 void __iomem *reg, u8 shift, u8 width, 331 u8 clk_divider_flags, const struct clk_div_table *table, 332 spinlock_t *lock); 333 334/** 335 * struct clk_mux - multiplexer clock 336 * 337 * @hw: handle between common and hardware-specific interfaces 338 * @reg: register controlling multiplexer 339 * @shift: shift to multiplexer bit field 340 * @width: width of mutliplexer bit field 341 * @flags: hardware-specific flags 342 * @lock: register lock 343 * 344 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 345 * and .recalc_rate 346 * 347 * Flags: 348 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 349 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 350 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 351 * register, and mask of mux bits are in higher 16-bit of this register. 352 * While setting the mux bits, higher 16-bit should also be updated to 353 * indicate changing mux bits. 354 */ 355struct clk_mux { 356 struct clk_hw hw; 357 void __iomem *reg; 358 u32 *table; 359 u32 mask; 360 u8 shift; 361 u8 flags; 362 spinlock_t *lock; 363}; 364 365#define CLK_MUX_INDEX_ONE BIT(0) 366#define CLK_MUX_INDEX_BIT BIT(1) 367#define CLK_MUX_HIWORD_MASK BIT(2) 368#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 369 370extern const struct clk_ops clk_mux_ops; 371extern const struct clk_ops clk_mux_ro_ops; 372 373struct clk *clk_register_mux(struct device *dev, const char *name, 374 const char **parent_names, u8 num_parents, unsigned long flags, 375 void __iomem *reg, u8 shift, u8 width, 376 u8 clk_mux_flags, spinlock_t *lock); 377 378struct clk *clk_register_mux_table(struct device *dev, const char *name, 379 const char **parent_names, u8 num_parents, unsigned long flags, 380 void __iomem *reg, u8 shift, u32 mask, 381 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 382 383void of_fixed_factor_clk_setup(struct device_node *node); 384 385/** 386 * struct clk_fixed_factor - fixed multiplier and divider clock 387 * 388 * @hw: handle between common and hardware-specific interfaces 389 * @mult: multiplier 390 * @div: divider 391 * 392 * Clock with a fixed multiplier and divider. The output frequency is the 393 * parent clock rate divided by div and multiplied by mult. 394 * Implements .recalc_rate, .set_rate and .round_rate 395 */ 396 397struct clk_fixed_factor { 398 struct clk_hw hw; 399 unsigned int mult; 400 unsigned int div; 401}; 402 403extern struct clk_ops clk_fixed_factor_ops; 404struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 405 const char *parent_name, unsigned long flags, 406 unsigned int mult, unsigned int div); 407 408/*** 409 * struct clk_composite - aggregate clock of mux, divider and gate clocks 410 * 411 * @hw: handle between common and hardware-specific interfaces 412 * @mux_hw: handle between composite and hardware-specific mux clock 413 * @rate_hw: handle between composite and hardware-specific rate clock 414 * @gate_hw: handle between composite and hardware-specific gate clock 415 * @mux_ops: clock ops for mux 416 * @rate_ops: clock ops for rate 417 * @gate_ops: clock ops for gate 418 */ 419struct clk_composite { 420 struct clk_hw hw; 421 struct clk_ops ops; 422 423 struct clk_hw *mux_hw; 424 struct clk_hw *rate_hw; 425 struct clk_hw *gate_hw; 426 427 const struct clk_ops *mux_ops; 428 const struct clk_ops *rate_ops; 429 const struct clk_ops *gate_ops; 430}; 431 432struct clk *clk_register_composite(struct device *dev, const char *name, 433 const char **parent_names, int num_parents, 434 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 435 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 436 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 437 unsigned long flags); 438 439/** 440 * clk_register - allocate a new clock, register it and return an opaque cookie 441 * @dev: device that is registering this clock 442 * @hw: link to hardware-specific clock data 443 * 444 * clk_register is the primary interface for populating the clock tree with new 445 * clock nodes. It returns a pointer to the newly allocated struct clk which 446 * cannot be dereferenced by driver code but may be used in conjuction with the 447 * rest of the clock API. In the event of an error clk_register will return an 448 * error code; drivers must test for an error code after calling clk_register. 449 */ 450struct clk *clk_register(struct device *dev, struct clk_hw *hw); 451struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 452 453void clk_unregister(struct clk *clk); 454void devm_clk_unregister(struct device *dev, struct clk *clk); 455 456/* helper functions */ 457const char *__clk_get_name(struct clk *clk); 458struct clk_hw *__clk_get_hw(struct clk *clk); 459u8 __clk_get_num_parents(struct clk *clk); 460struct clk *__clk_get_parent(struct clk *clk); 461struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); 462unsigned int __clk_get_enable_count(struct clk *clk); 463unsigned int __clk_get_prepare_count(struct clk *clk); 464unsigned long __clk_get_rate(struct clk *clk); 465unsigned long __clk_get_accuracy(struct clk *clk); 466unsigned long __clk_get_flags(struct clk *clk); 467bool __clk_is_prepared(struct clk *clk); 468bool __clk_is_enabled(struct clk *clk); 469struct clk *__clk_lookup(const char *name); 470long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 471 unsigned long *best_parent_rate, 472 struct clk **best_parent_p); 473 474/* 475 * FIXME clock api without lock protection 476 */ 477int __clk_prepare(struct clk *clk); 478void __clk_unprepare(struct clk *clk); 479void __clk_reparent(struct clk *clk, struct clk *new_parent); 480unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 481 482struct of_device_id; 483 484typedef void (*of_clk_init_cb_t)(struct device_node *); 485 486struct clk_onecell_data { 487 struct clk **clks; 488 unsigned int clk_num; 489}; 490 491#define CLK_OF_DECLARE(name, compat, fn) \ 492 static const struct of_device_id __clk_of_table_##name \ 493 __used __section(__clk_of_table) \ 494 = { .compatible = compat, .data = fn }; 495 496#ifdef CONFIG_OF 497int of_clk_add_provider(struct device_node *np, 498 struct clk *(*clk_src_get)(struct of_phandle_args *args, 499 void *data), 500 void *data); 501void of_clk_del_provider(struct device_node *np); 502struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 503 void *data); 504struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 505int of_clk_get_parent_count(struct device_node *np); 506const char *of_clk_get_parent_name(struct device_node *np, int index); 507 508void of_clk_init(const struct of_device_id *matches); 509 510#else /* !CONFIG_OF */ 511 512static inline int of_clk_add_provider(struct device_node *np, 513 struct clk *(*clk_src_get)(struct of_phandle_args *args, 514 void *data), 515 void *data) 516{ 517 return 0; 518} 519#define of_clk_del_provider(np) \ 520 { while (0); } 521static inline struct clk *of_clk_src_simple_get( 522 struct of_phandle_args *clkspec, void *data) 523{ 524 return ERR_PTR(-ENOENT); 525} 526static inline struct clk *of_clk_src_onecell_get( 527 struct of_phandle_args *clkspec, void *data) 528{ 529 return ERR_PTR(-ENOENT); 530} 531static inline const char *of_clk_get_parent_name(struct device_node *np, 532 int index) 533{ 534 return NULL; 535} 536#define of_clk_init(matches) \ 537 { while (0); } 538#endif /* CONFIG_OF */ 539 540/* 541 * wrap access to peripherals in accessor routines 542 * for improved portability across platforms 543 */ 544 545static inline u32 clk_readl(u32 __iomem *reg) 546{ 547 return readl(reg); 548} 549 550static inline void clk_writel(u32 val, u32 __iomem *reg) 551{ 552 writel(val, reg); 553} 554 555#endif /* CONFIG_COMMON_CLK */ 556#endif /* CLK_PROVIDER_H */ 557