clk-provider.h revision 5279fc402ae59361a224d641d5823b21b4206232
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15#include <linux/io.h> 16 17#ifdef CONFIG_COMMON_CLK 18 19/* 20 * flags used across common struct clk. these flags should only affect the 21 * top-level framework. custom flags for dealing with hardware specifics 22 * belong in struct clk_foo 23 */ 24#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 25#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 26#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 27#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 28#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 29#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 30#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 31#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 32#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 33 34struct clk_hw; 35 36/** 37 * struct clk_ops - Callback operations for hardware clocks; these are to 38 * be provided by the clock implementation, and will be called by drivers 39 * through the clk_* api. 40 * 41 * @prepare: Prepare the clock for enabling. This must not return until 42 * the clock is fully prepared, and it's safe to call clk_enable. 43 * This callback is intended to allow clock implementations to 44 * do any initialisation that may sleep. Called with 45 * prepare_lock held. 46 * 47 * @unprepare: Release the clock from its prepared state. This will typically 48 * undo any work done in the @prepare callback. Called with 49 * prepare_lock held. 50 * 51 * @is_prepared: Queries the hardware to determine if the clock is prepared. 52 * This function is allowed to sleep. Optional, if this op is not 53 * set then the prepare count will be used. 54 * 55 * @unprepare_unused: Unprepare the clock atomically. Only called from 56 * clk_disable_unused for prepare clocks with special needs. 57 * Called with prepare mutex held. This function may sleep. 58 * 59 * @enable: Enable the clock atomically. This must not return until the 60 * clock is generating a valid clock signal, usable by consumer 61 * devices. Called with enable_lock held. This function must not 62 * sleep. 63 * 64 * @disable: Disable the clock atomically. Called with enable_lock held. 65 * This function must not sleep. 66 * 67 * @is_enabled: Queries the hardware to determine if the clock is enabled. 68 * This function must not sleep. Optional, if this op is not 69 * set then the enable count will be used. 70 * 71 * @disable_unused: Disable the clock atomically. Only called from 72 * clk_disable_unused for gate clocks with special needs. 73 * Called with enable_lock held. This function must not 74 * sleep. 75 * 76 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 77 * parent rate is an input parameter. It is up to the caller to 78 * ensure that the prepare_mutex is held across this call. 79 * Returns the calculated rate. Optional, but recommended - if 80 * this op is not set then clock rate will be initialized to 0. 81 * 82 * @round_rate: Given a target rate as input, returns the closest rate actually 83 * supported by the clock. 84 * 85 * @determine_rate: Given a target rate as input, returns the closest rate 86 * actually supported by the clock, and optionally the parent clock 87 * that should be used to provide the clock rate. 88 * 89 * @get_parent: Queries the hardware to determine the parent of a clock. The 90 * return value is a u8 which specifies the index corresponding to 91 * the parent clock. This index can be applied to either the 92 * .parent_names or .parents arrays. In short, this function 93 * translates the parent value read from hardware into an array 94 * index. Currently only called when the clock is initialized by 95 * __clk_init. This callback is mandatory for clocks with 96 * multiple parents. It is optional (and unnecessary) for clocks 97 * with 0 or 1 parents. 98 * 99 * @set_parent: Change the input source of this clock; for clocks with multiple 100 * possible parents specify a new parent by passing in the index 101 * as a u8 corresponding to the parent in either the .parent_names 102 * or .parents arrays. This function in affect translates an 103 * array index into the value programmed into the hardware. 104 * Returns 0 on success, -EERROR otherwise. 105 * 106 * @set_rate: Change the rate of this clock. The requested rate is specified 107 * by the second argument, which should typically be the return 108 * of .round_rate call. The third argument gives the parent rate 109 * which is likely helpful for most .set_rate implementation. 110 * Returns 0 on success, -EERROR otherwise. 111 * 112 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 113 * is expressed in ppb (parts per billion). The parent accuracy is 114 * an input parameter. 115 * Returns the calculated accuracy. Optional - if this op is not 116 * set then clock accuracy will be initialized to parent accuracy 117 * or 0 (perfect clock) if clock has no parent. 118 * 119 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 120 * implementations to split any work between atomic (enable) and sleepable 121 * (prepare) contexts. If enabling a clock requires code that might sleep, 122 * this must be done in clk_prepare. Clock enable code that will never be 123 * called in a sleepable context may be implemented in clk_enable. 124 * 125 * Typically, drivers will call clk_prepare when a clock may be needed later 126 * (eg. when a device is opened), and clk_enable when the clock is actually 127 * required (eg. from an interrupt). Note that clk_prepare MUST have been 128 * called before clk_enable. 129 */ 130struct clk_ops { 131 int (*prepare)(struct clk_hw *hw); 132 void (*unprepare)(struct clk_hw *hw); 133 int (*is_prepared)(struct clk_hw *hw); 134 void (*unprepare_unused)(struct clk_hw *hw); 135 int (*enable)(struct clk_hw *hw); 136 void (*disable)(struct clk_hw *hw); 137 int (*is_enabled)(struct clk_hw *hw); 138 void (*disable_unused)(struct clk_hw *hw); 139 unsigned long (*recalc_rate)(struct clk_hw *hw, 140 unsigned long parent_rate); 141 long (*round_rate)(struct clk_hw *hw, unsigned long, 142 unsigned long *); 143 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 144 unsigned long *best_parent_rate, 145 struct clk **best_parent_clk); 146 int (*set_parent)(struct clk_hw *hw, u8 index); 147 u8 (*get_parent)(struct clk_hw *hw); 148 int (*set_rate)(struct clk_hw *hw, unsigned long, 149 unsigned long); 150 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 151 unsigned long parent_accuracy); 152 void (*init)(struct clk_hw *hw); 153}; 154 155/** 156 * struct clk_init_data - holds init data that's common to all clocks and is 157 * shared between the clock provider and the common clock framework. 158 * 159 * @name: clock name 160 * @ops: operations this clock supports 161 * @parent_names: array of string names for all possible parents 162 * @num_parents: number of possible parents 163 * @flags: framework-level hints and quirks 164 */ 165struct clk_init_data { 166 const char *name; 167 const struct clk_ops *ops; 168 const char **parent_names; 169 u8 num_parents; 170 unsigned long flags; 171}; 172 173/** 174 * struct clk_hw - handle for traversing from a struct clk to its corresponding 175 * hardware-specific structure. struct clk_hw should be declared within struct 176 * clk_foo and then referenced by the struct clk instance that uses struct 177 * clk_foo's clk_ops 178 * 179 * @clk: pointer to the struct clk instance that points back to this struct 180 * clk_hw instance 181 * 182 * @init: pointer to struct clk_init_data that contains the init data shared 183 * with the common clock framework. 184 */ 185struct clk_hw { 186 struct clk *clk; 187 const struct clk_init_data *init; 188}; 189 190/* 191 * DOC: Basic clock implementations common to many platforms 192 * 193 * Each basic clock hardware type is comprised of a structure describing the 194 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 195 * unique flags for that hardware type, a registration function and an 196 * alternative macro for static initialization 197 */ 198 199/** 200 * struct clk_fixed_rate - fixed-rate clock 201 * @hw: handle between common and hardware-specific interfaces 202 * @fixed_rate: constant frequency of clock 203 */ 204struct clk_fixed_rate { 205 struct clk_hw hw; 206 unsigned long fixed_rate; 207 u8 flags; 208}; 209 210extern const struct clk_ops clk_fixed_rate_ops; 211struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 212 const char *parent_name, unsigned long flags, 213 unsigned long fixed_rate); 214 215void of_fixed_clk_setup(struct device_node *np); 216 217/** 218 * struct clk_gate - gating clock 219 * 220 * @hw: handle between common and hardware-specific interfaces 221 * @reg: register controlling gate 222 * @bit_idx: single bit controlling gate 223 * @flags: hardware-specific flags 224 * @lock: register lock 225 * 226 * Clock which can gate its output. Implements .enable & .disable 227 * 228 * Flags: 229 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 230 * enable the clock. Setting this flag does the opposite: setting the bit 231 * disable the clock and clearing it enables the clock 232 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 233 * of this register, and mask of gate bits are in higher 16-bit of this 234 * register. While setting the gate bits, higher 16-bit should also be 235 * updated to indicate changing gate bits. 236 */ 237struct clk_gate { 238 struct clk_hw hw; 239 void __iomem *reg; 240 u8 bit_idx; 241 u8 flags; 242 spinlock_t *lock; 243}; 244 245#define CLK_GATE_SET_TO_DISABLE BIT(0) 246#define CLK_GATE_HIWORD_MASK BIT(1) 247 248extern const struct clk_ops clk_gate_ops; 249struct clk *clk_register_gate(struct device *dev, const char *name, 250 const char *parent_name, unsigned long flags, 251 void __iomem *reg, u8 bit_idx, 252 u8 clk_gate_flags, spinlock_t *lock); 253 254struct clk_div_table { 255 unsigned int val; 256 unsigned int div; 257}; 258 259/** 260 * struct clk_divider - adjustable divider clock 261 * 262 * @hw: handle between common and hardware-specific interfaces 263 * @reg: register containing the divider 264 * @shift: shift to the divider bit field 265 * @width: width of the divider bit field 266 * @table: array of value/divider pairs, last entry should have div = 0 267 * @lock: register lock 268 * 269 * Clock with an adjustable divider affecting its output frequency. Implements 270 * .recalc_rate, .set_rate and .round_rate 271 * 272 * Flags: 273 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 274 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 275 * the raw value read from the register, with the value of zero considered 276 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 277 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 278 * the hardware register 279 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 280 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 281 * Some hardware implementations gracefully handle this case and allow a 282 * zero divisor by not modifying their input clock 283 * (divide by one / bypass). 284 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 285 * of this register, and mask of divider bits are in higher 16-bit of this 286 * register. While setting the divider bits, higher 16-bit should also be 287 * updated to indicate changing divider bits. 288 */ 289struct clk_divider { 290 struct clk_hw hw; 291 void __iomem *reg; 292 u8 shift; 293 u8 width; 294 u8 flags; 295 const struct clk_div_table *table; 296 spinlock_t *lock; 297}; 298 299#define CLK_DIVIDER_ONE_BASED BIT(0) 300#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 301#define CLK_DIVIDER_ALLOW_ZERO BIT(2) 302#define CLK_DIVIDER_HIWORD_MASK BIT(3) 303 304extern const struct clk_ops clk_divider_ops; 305struct clk *clk_register_divider(struct device *dev, const char *name, 306 const char *parent_name, unsigned long flags, 307 void __iomem *reg, u8 shift, u8 width, 308 u8 clk_divider_flags, spinlock_t *lock); 309struct clk *clk_register_divider_table(struct device *dev, const char *name, 310 const char *parent_name, unsigned long flags, 311 void __iomem *reg, u8 shift, u8 width, 312 u8 clk_divider_flags, const struct clk_div_table *table, 313 spinlock_t *lock); 314 315/** 316 * struct clk_mux - multiplexer clock 317 * 318 * @hw: handle between common and hardware-specific interfaces 319 * @reg: register controlling multiplexer 320 * @shift: shift to multiplexer bit field 321 * @width: width of mutliplexer bit field 322 * @flags: hardware-specific flags 323 * @lock: register lock 324 * 325 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 326 * and .recalc_rate 327 * 328 * Flags: 329 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 330 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 331 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 332 * register, and mask of mux bits are in higher 16-bit of this register. 333 * While setting the mux bits, higher 16-bit should also be updated to 334 * indicate changing mux bits. 335 */ 336struct clk_mux { 337 struct clk_hw hw; 338 void __iomem *reg; 339 u32 *table; 340 u32 mask; 341 u8 shift; 342 u8 flags; 343 spinlock_t *lock; 344}; 345 346#define CLK_MUX_INDEX_ONE BIT(0) 347#define CLK_MUX_INDEX_BIT BIT(1) 348#define CLK_MUX_HIWORD_MASK BIT(2) 349#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 350 351extern const struct clk_ops clk_mux_ops; 352extern const struct clk_ops clk_mux_ro_ops; 353 354struct clk *clk_register_mux(struct device *dev, const char *name, 355 const char **parent_names, u8 num_parents, unsigned long flags, 356 void __iomem *reg, u8 shift, u8 width, 357 u8 clk_mux_flags, spinlock_t *lock); 358 359struct clk *clk_register_mux_table(struct device *dev, const char *name, 360 const char **parent_names, u8 num_parents, unsigned long flags, 361 void __iomem *reg, u8 shift, u32 mask, 362 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 363 364void of_fixed_factor_clk_setup(struct device_node *node); 365 366/** 367 * struct clk_fixed_factor - fixed multiplier and divider clock 368 * 369 * @hw: handle between common and hardware-specific interfaces 370 * @mult: multiplier 371 * @div: divider 372 * 373 * Clock with a fixed multiplier and divider. The output frequency is the 374 * parent clock rate divided by div and multiplied by mult. 375 * Implements .recalc_rate, .set_rate and .round_rate 376 */ 377 378struct clk_fixed_factor { 379 struct clk_hw hw; 380 unsigned int mult; 381 unsigned int div; 382}; 383 384extern struct clk_ops clk_fixed_factor_ops; 385struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 386 const char *parent_name, unsigned long flags, 387 unsigned int mult, unsigned int div); 388 389/*** 390 * struct clk_composite - aggregate clock of mux, divider and gate clocks 391 * 392 * @hw: handle between common and hardware-specific interfaces 393 * @mux_hw: handle between composite and hardware-specific mux clock 394 * @rate_hw: handle between composite and hardware-specific rate clock 395 * @gate_hw: handle between composite and hardware-specific gate clock 396 * @mux_ops: clock ops for mux 397 * @rate_ops: clock ops for rate 398 * @gate_ops: clock ops for gate 399 */ 400struct clk_composite { 401 struct clk_hw hw; 402 struct clk_ops ops; 403 404 struct clk_hw *mux_hw; 405 struct clk_hw *rate_hw; 406 struct clk_hw *gate_hw; 407 408 const struct clk_ops *mux_ops; 409 const struct clk_ops *rate_ops; 410 const struct clk_ops *gate_ops; 411}; 412 413struct clk *clk_register_composite(struct device *dev, const char *name, 414 const char **parent_names, int num_parents, 415 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 416 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 417 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 418 unsigned long flags); 419 420/** 421 * clk_register - allocate a new clock, register it and return an opaque cookie 422 * @dev: device that is registering this clock 423 * @hw: link to hardware-specific clock data 424 * 425 * clk_register is the primary interface for populating the clock tree with new 426 * clock nodes. It returns a pointer to the newly allocated struct clk which 427 * cannot be dereferenced by driver code but may be used in conjuction with the 428 * rest of the clock API. In the event of an error clk_register will return an 429 * error code; drivers must test for an error code after calling clk_register. 430 */ 431struct clk *clk_register(struct device *dev, struct clk_hw *hw); 432struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 433 434void clk_unregister(struct clk *clk); 435void devm_clk_unregister(struct device *dev, struct clk *clk); 436 437/* helper functions */ 438const char *__clk_get_name(struct clk *clk); 439struct clk_hw *__clk_get_hw(struct clk *clk); 440u8 __clk_get_num_parents(struct clk *clk); 441struct clk *__clk_get_parent(struct clk *clk); 442struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); 443unsigned int __clk_get_enable_count(struct clk *clk); 444unsigned int __clk_get_prepare_count(struct clk *clk); 445unsigned long __clk_get_rate(struct clk *clk); 446unsigned long __clk_get_accuracy(struct clk *clk); 447unsigned long __clk_get_flags(struct clk *clk); 448bool __clk_is_prepared(struct clk *clk); 449bool __clk_is_enabled(struct clk *clk); 450struct clk *__clk_lookup(const char *name); 451long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 452 unsigned long *best_parent_rate, 453 struct clk **best_parent_p); 454 455/* 456 * FIXME clock api without lock protection 457 */ 458int __clk_prepare(struct clk *clk); 459void __clk_unprepare(struct clk *clk); 460void __clk_reparent(struct clk *clk, struct clk *new_parent); 461unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 462 463struct of_device_id; 464 465typedef void (*of_clk_init_cb_t)(struct device_node *); 466 467struct clk_onecell_data { 468 struct clk **clks; 469 unsigned int clk_num; 470}; 471 472#define CLK_OF_DECLARE(name, compat, fn) \ 473 static const struct of_device_id __clk_of_table_##name \ 474 __used __section(__clk_of_table) \ 475 = { .compatible = compat, .data = fn }; 476 477#ifdef CONFIG_OF 478int of_clk_add_provider(struct device_node *np, 479 struct clk *(*clk_src_get)(struct of_phandle_args *args, 480 void *data), 481 void *data); 482void of_clk_del_provider(struct device_node *np); 483struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 484 void *data); 485struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 486int of_clk_get_parent_count(struct device_node *np); 487const char *of_clk_get_parent_name(struct device_node *np, int index); 488 489void of_clk_init(const struct of_device_id *matches); 490 491#else /* !CONFIG_OF */ 492 493static inline int of_clk_add_provider(struct device_node *np, 494 struct clk *(*clk_src_get)(struct of_phandle_args *args, 495 void *data), 496 void *data) 497{ 498 return 0; 499} 500#define of_clk_del_provider(np) \ 501 { while (0); } 502static inline struct clk *of_clk_src_simple_get( 503 struct of_phandle_args *clkspec, void *data) 504{ 505 return ERR_PTR(-ENOENT); 506} 507static inline struct clk *of_clk_src_onecell_get( 508 struct of_phandle_args *clkspec, void *data) 509{ 510 return ERR_PTR(-ENOENT); 511} 512static inline const char *of_clk_get_parent_name(struct device_node *np, 513 int index) 514{ 515 return NULL; 516} 517#define of_clk_init(matches) \ 518 { while (0); } 519#endif /* CONFIG_OF */ 520 521/* 522 * wrap access to peripherals in accessor routines 523 * for improved portability across platforms 524 */ 525 526static inline u32 clk_readl(u32 __iomem *reg) 527{ 528 return readl(reg); 529} 530 531static inline void clk_writel(u32 val, u32 __iomem *reg) 532{ 533 writel(val, reg); 534} 535 536#endif /* CONFIG_COMMON_CLK */ 537#endif /* CLK_PROVIDER_H */ 538