clk-provider.h revision 54196ccbe0ba1f268a646059473313589db35b01
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15#include <linux/io.h> 16 17#ifdef CONFIG_COMMON_CLK 18 19/* 20 * flags used across common struct clk. these flags should only affect the 21 * top-level framework. custom flags for dealing with hardware specifics 22 * belong in struct clk_foo 23 */ 24#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 25#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 26#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 27#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 28#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 29#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 30#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 31#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 32#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ 33 34struct clk_hw; 35struct dentry; 36 37/** 38 * struct clk_ops - Callback operations for hardware clocks; these are to 39 * be provided by the clock implementation, and will be called by drivers 40 * through the clk_* api. 41 * 42 * @prepare: Prepare the clock for enabling. This must not return until 43 * the clock is fully prepared, and it's safe to call clk_enable. 44 * This callback is intended to allow clock implementations to 45 * do any initialisation that may sleep. Called with 46 * prepare_lock held. 47 * 48 * @unprepare: Release the clock from its prepared state. This will typically 49 * undo any work done in the @prepare callback. Called with 50 * prepare_lock held. 51 * 52 * @is_prepared: Queries the hardware to determine if the clock is prepared. 53 * This function is allowed to sleep. Optional, if this op is not 54 * set then the prepare count will be used. 55 * 56 * @unprepare_unused: Unprepare the clock atomically. Only called from 57 * clk_disable_unused for prepare clocks with special needs. 58 * Called with prepare mutex held. This function may sleep. 59 * 60 * @enable: Enable the clock atomically. This must not return until the 61 * clock is generating a valid clock signal, usable by consumer 62 * devices. Called with enable_lock held. This function must not 63 * sleep. 64 * 65 * @disable: Disable the clock atomically. Called with enable_lock held. 66 * This function must not sleep. 67 * 68 * @is_enabled: Queries the hardware to determine if the clock is enabled. 69 * This function must not sleep. Optional, if this op is not 70 * set then the enable count will be used. 71 * 72 * @disable_unused: Disable the clock atomically. Only called from 73 * clk_disable_unused for gate clocks with special needs. 74 * Called with enable_lock held. This function must not 75 * sleep. 76 * 77 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 78 * parent rate is an input parameter. It is up to the caller to 79 * ensure that the prepare_mutex is held across this call. 80 * Returns the calculated rate. Optional, but recommended - if 81 * this op is not set then clock rate will be initialized to 0. 82 * 83 * @round_rate: Given a target rate as input, returns the closest rate actually 84 * supported by the clock. 85 * 86 * @determine_rate: Given a target rate as input, returns the closest rate 87 * actually supported by the clock, and optionally the parent clock 88 * that should be used to provide the clock rate. 89 * 90 * @get_parent: Queries the hardware to determine the parent of a clock. The 91 * return value is a u8 which specifies the index corresponding to 92 * the parent clock. This index can be applied to either the 93 * .parent_names or .parents arrays. In short, this function 94 * translates the parent value read from hardware into an array 95 * index. Currently only called when the clock is initialized by 96 * __clk_init. This callback is mandatory for clocks with 97 * multiple parents. It is optional (and unnecessary) for clocks 98 * with 0 or 1 parents. 99 * 100 * @set_parent: Change the input source of this clock; for clocks with multiple 101 * possible parents specify a new parent by passing in the index 102 * as a u8 corresponding to the parent in either the .parent_names 103 * or .parents arrays. This function in affect translates an 104 * array index into the value programmed into the hardware. 105 * Returns 0 on success, -EERROR otherwise. 106 * 107 * @set_rate: Change the rate of this clock. The requested rate is specified 108 * by the second argument, which should typically be the return 109 * of .round_rate call. The third argument gives the parent rate 110 * which is likely helpful for most .set_rate implementation. 111 * Returns 0 on success, -EERROR otherwise. 112 * 113 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy 114 * is expressed in ppb (parts per billion). The parent accuracy is 115 * an input parameter. 116 * Returns the calculated accuracy. Optional - if this op is not 117 * set then clock accuracy will be initialized to parent accuracy 118 * or 0 (perfect clock) if clock has no parent. 119 * 120 * @set_rate_and_parent: Change the rate and the parent of this clock. The 121 * requested rate is specified by the second argument, which 122 * should typically be the return of .round_rate call. The 123 * third argument gives the parent rate which is likely helpful 124 * for most .set_rate_and_parent implementation. The fourth 125 * argument gives the parent index. This callback is optional (and 126 * unnecessary) for clocks with 0 or 1 parents as well as 127 * for clocks that can tolerate switching the rate and the parent 128 * separately via calls to .set_parent and .set_rate. 129 * Returns 0 on success, -EERROR otherwise. 130 * 131 * @debug_init: Set up type-specific debugfs entries for this clock. This 132 * is called once, after the debugfs directory entry for this 133 * clock has been created. The dentry pointer representing that 134 * directory is provided as an argument. Called with 135 * prepare_lock held. Returns 0 on success, -EERROR otherwise. 136 * 137 * 138 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 139 * implementations to split any work between atomic (enable) and sleepable 140 * (prepare) contexts. If enabling a clock requires code that might sleep, 141 * this must be done in clk_prepare. Clock enable code that will never be 142 * called in a sleepable context may be implemented in clk_enable. 143 * 144 * Typically, drivers will call clk_prepare when a clock may be needed later 145 * (eg. when a device is opened), and clk_enable when the clock is actually 146 * required (eg. from an interrupt). Note that clk_prepare MUST have been 147 * called before clk_enable. 148 */ 149struct clk_ops { 150 int (*prepare)(struct clk_hw *hw); 151 void (*unprepare)(struct clk_hw *hw); 152 int (*is_prepared)(struct clk_hw *hw); 153 void (*unprepare_unused)(struct clk_hw *hw); 154 int (*enable)(struct clk_hw *hw); 155 void (*disable)(struct clk_hw *hw); 156 int (*is_enabled)(struct clk_hw *hw); 157 void (*disable_unused)(struct clk_hw *hw); 158 unsigned long (*recalc_rate)(struct clk_hw *hw, 159 unsigned long parent_rate); 160 long (*round_rate)(struct clk_hw *hw, unsigned long, 161 unsigned long *); 162 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 163 unsigned long *best_parent_rate, 164 struct clk **best_parent_clk); 165 int (*set_parent)(struct clk_hw *hw, u8 index); 166 u8 (*get_parent)(struct clk_hw *hw); 167 int (*set_rate)(struct clk_hw *hw, unsigned long, 168 unsigned long); 169 int (*set_rate_and_parent)(struct clk_hw *hw, 170 unsigned long rate, 171 unsigned long parent_rate, u8 index); 172 unsigned long (*recalc_accuracy)(struct clk_hw *hw, 173 unsigned long parent_accuracy); 174 void (*init)(struct clk_hw *hw); 175 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry); 176}; 177 178/** 179 * struct clk_init_data - holds init data that's common to all clocks and is 180 * shared between the clock provider and the common clock framework. 181 * 182 * @name: clock name 183 * @ops: operations this clock supports 184 * @parent_names: array of string names for all possible parents 185 * @num_parents: number of possible parents 186 * @flags: framework-level hints and quirks 187 */ 188struct clk_init_data { 189 const char *name; 190 const struct clk_ops *ops; 191 const char **parent_names; 192 u8 num_parents; 193 unsigned long flags; 194}; 195 196/** 197 * struct clk_hw - handle for traversing from a struct clk to its corresponding 198 * hardware-specific structure. struct clk_hw should be declared within struct 199 * clk_foo and then referenced by the struct clk instance that uses struct 200 * clk_foo's clk_ops 201 * 202 * @clk: pointer to the struct clk instance that points back to this struct 203 * clk_hw instance 204 * 205 * @init: pointer to struct clk_init_data that contains the init data shared 206 * with the common clock framework. 207 */ 208struct clk_hw { 209 struct clk *clk; 210 const struct clk_init_data *init; 211}; 212 213/* 214 * DOC: Basic clock implementations common to many platforms 215 * 216 * Each basic clock hardware type is comprised of a structure describing the 217 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 218 * unique flags for that hardware type, a registration function and an 219 * alternative macro for static initialization 220 */ 221 222/** 223 * struct clk_fixed_rate - fixed-rate clock 224 * @hw: handle between common and hardware-specific interfaces 225 * @fixed_rate: constant frequency of clock 226 */ 227struct clk_fixed_rate { 228 struct clk_hw hw; 229 unsigned long fixed_rate; 230 unsigned long fixed_accuracy; 231 u8 flags; 232}; 233 234extern const struct clk_ops clk_fixed_rate_ops; 235struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 236 const char *parent_name, unsigned long flags, 237 unsigned long fixed_rate); 238struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev, 239 const char *name, const char *parent_name, unsigned long flags, 240 unsigned long fixed_rate, unsigned long fixed_accuracy); 241 242void of_fixed_clk_setup(struct device_node *np); 243 244/** 245 * struct clk_gate - gating clock 246 * 247 * @hw: handle between common and hardware-specific interfaces 248 * @reg: register controlling gate 249 * @bit_idx: single bit controlling gate 250 * @flags: hardware-specific flags 251 * @lock: register lock 252 * 253 * Clock which can gate its output. Implements .enable & .disable 254 * 255 * Flags: 256 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 257 * enable the clock. Setting this flag does the opposite: setting the bit 258 * disable the clock and clearing it enables the clock 259 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 260 * of this register, and mask of gate bits are in higher 16-bit of this 261 * register. While setting the gate bits, higher 16-bit should also be 262 * updated to indicate changing gate bits. 263 */ 264struct clk_gate { 265 struct clk_hw hw; 266 void __iomem *reg; 267 u8 bit_idx; 268 u8 flags; 269 spinlock_t *lock; 270}; 271 272#define CLK_GATE_SET_TO_DISABLE BIT(0) 273#define CLK_GATE_HIWORD_MASK BIT(1) 274 275extern const struct clk_ops clk_gate_ops; 276struct clk *clk_register_gate(struct device *dev, const char *name, 277 const char *parent_name, unsigned long flags, 278 void __iomem *reg, u8 bit_idx, 279 u8 clk_gate_flags, spinlock_t *lock); 280 281struct clk_div_table { 282 unsigned int val; 283 unsigned int div; 284}; 285 286/** 287 * struct clk_divider - adjustable divider clock 288 * 289 * @hw: handle between common and hardware-specific interfaces 290 * @reg: register containing the divider 291 * @shift: shift to the divider bit field 292 * @width: width of the divider bit field 293 * @table: array of value/divider pairs, last entry should have div = 0 294 * @lock: register lock 295 * 296 * Clock with an adjustable divider affecting its output frequency. Implements 297 * .recalc_rate, .set_rate and .round_rate 298 * 299 * Flags: 300 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 301 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 302 * the raw value read from the register, with the value of zero considered 303 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 304 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 305 * the hardware register 306 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 307 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 308 * Some hardware implementations gracefully handle this case and allow a 309 * zero divisor by not modifying their input clock 310 * (divide by one / bypass). 311 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 312 * of this register, and mask of divider bits are in higher 16-bit of this 313 * register. While setting the divider bits, higher 16-bit should also be 314 * updated to indicate changing divider bits. 315 */ 316struct clk_divider { 317 struct clk_hw hw; 318 void __iomem *reg; 319 u8 shift; 320 u8 width; 321 u8 flags; 322 const struct clk_div_table *table; 323 spinlock_t *lock; 324}; 325 326#define CLK_DIVIDER_ONE_BASED BIT(0) 327#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 328#define CLK_DIVIDER_ALLOW_ZERO BIT(2) 329#define CLK_DIVIDER_HIWORD_MASK BIT(3) 330 331extern const struct clk_ops clk_divider_ops; 332struct clk *clk_register_divider(struct device *dev, const char *name, 333 const char *parent_name, unsigned long flags, 334 void __iomem *reg, u8 shift, u8 width, 335 u8 clk_divider_flags, spinlock_t *lock); 336struct clk *clk_register_divider_table(struct device *dev, const char *name, 337 const char *parent_name, unsigned long flags, 338 void __iomem *reg, u8 shift, u8 width, 339 u8 clk_divider_flags, const struct clk_div_table *table, 340 spinlock_t *lock); 341 342/** 343 * struct clk_mux - multiplexer clock 344 * 345 * @hw: handle between common and hardware-specific interfaces 346 * @reg: register controlling multiplexer 347 * @shift: shift to multiplexer bit field 348 * @width: width of mutliplexer bit field 349 * @flags: hardware-specific flags 350 * @lock: register lock 351 * 352 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 353 * and .recalc_rate 354 * 355 * Flags: 356 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 357 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 358 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 359 * register, and mask of mux bits are in higher 16-bit of this register. 360 * While setting the mux bits, higher 16-bit should also be updated to 361 * indicate changing mux bits. 362 */ 363struct clk_mux { 364 struct clk_hw hw; 365 void __iomem *reg; 366 u32 *table; 367 u32 mask; 368 u8 shift; 369 u8 flags; 370 spinlock_t *lock; 371}; 372 373#define CLK_MUX_INDEX_ONE BIT(0) 374#define CLK_MUX_INDEX_BIT BIT(1) 375#define CLK_MUX_HIWORD_MASK BIT(2) 376#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 377 378extern const struct clk_ops clk_mux_ops; 379extern const struct clk_ops clk_mux_ro_ops; 380 381struct clk *clk_register_mux(struct device *dev, const char *name, 382 const char **parent_names, u8 num_parents, unsigned long flags, 383 void __iomem *reg, u8 shift, u8 width, 384 u8 clk_mux_flags, spinlock_t *lock); 385 386struct clk *clk_register_mux_table(struct device *dev, const char *name, 387 const char **parent_names, u8 num_parents, unsigned long flags, 388 void __iomem *reg, u8 shift, u32 mask, 389 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 390 391void of_fixed_factor_clk_setup(struct device_node *node); 392 393/** 394 * struct clk_fixed_factor - fixed multiplier and divider clock 395 * 396 * @hw: handle between common and hardware-specific interfaces 397 * @mult: multiplier 398 * @div: divider 399 * 400 * Clock with a fixed multiplier and divider. The output frequency is the 401 * parent clock rate divided by div and multiplied by mult. 402 * Implements .recalc_rate, .set_rate and .round_rate 403 */ 404 405struct clk_fixed_factor { 406 struct clk_hw hw; 407 unsigned int mult; 408 unsigned int div; 409}; 410 411extern struct clk_ops clk_fixed_factor_ops; 412struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 413 const char *parent_name, unsigned long flags, 414 unsigned int mult, unsigned int div); 415 416/*** 417 * struct clk_composite - aggregate clock of mux, divider and gate clocks 418 * 419 * @hw: handle between common and hardware-specific interfaces 420 * @mux_hw: handle between composite and hardware-specific mux clock 421 * @rate_hw: handle between composite and hardware-specific rate clock 422 * @gate_hw: handle between composite and hardware-specific gate clock 423 * @mux_ops: clock ops for mux 424 * @rate_ops: clock ops for rate 425 * @gate_ops: clock ops for gate 426 */ 427struct clk_composite { 428 struct clk_hw hw; 429 struct clk_ops ops; 430 431 struct clk_hw *mux_hw; 432 struct clk_hw *rate_hw; 433 struct clk_hw *gate_hw; 434 435 const struct clk_ops *mux_ops; 436 const struct clk_ops *rate_ops; 437 const struct clk_ops *gate_ops; 438}; 439 440struct clk *clk_register_composite(struct device *dev, const char *name, 441 const char **parent_names, int num_parents, 442 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 443 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 444 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 445 unsigned long flags); 446 447/** 448 * clk_register - allocate a new clock, register it and return an opaque cookie 449 * @dev: device that is registering this clock 450 * @hw: link to hardware-specific clock data 451 * 452 * clk_register is the primary interface for populating the clock tree with new 453 * clock nodes. It returns a pointer to the newly allocated struct clk which 454 * cannot be dereferenced by driver code but may be used in conjuction with the 455 * rest of the clock API. In the event of an error clk_register will return an 456 * error code; drivers must test for an error code after calling clk_register. 457 */ 458struct clk *clk_register(struct device *dev, struct clk_hw *hw); 459struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 460 461void clk_unregister(struct clk *clk); 462void devm_clk_unregister(struct device *dev, struct clk *clk); 463 464/* helper functions */ 465const char *__clk_get_name(struct clk *clk); 466struct clk_hw *__clk_get_hw(struct clk *clk); 467u8 __clk_get_num_parents(struct clk *clk); 468struct clk *__clk_get_parent(struct clk *clk); 469struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); 470unsigned int __clk_get_enable_count(struct clk *clk); 471unsigned int __clk_get_prepare_count(struct clk *clk); 472unsigned long __clk_get_rate(struct clk *clk); 473unsigned long __clk_get_accuracy(struct clk *clk); 474unsigned long __clk_get_flags(struct clk *clk); 475bool __clk_is_prepared(struct clk *clk); 476bool __clk_is_enabled(struct clk *clk); 477struct clk *__clk_lookup(const char *name); 478long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate, 479 unsigned long *best_parent_rate, 480 struct clk **best_parent_p); 481 482/* 483 * FIXME clock api without lock protection 484 */ 485int __clk_prepare(struct clk *clk); 486void __clk_unprepare(struct clk *clk); 487void __clk_reparent(struct clk *clk, struct clk *new_parent); 488unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 489 490struct of_device_id; 491 492typedef void (*of_clk_init_cb_t)(struct device_node *); 493 494struct clk_onecell_data { 495 struct clk **clks; 496 unsigned int clk_num; 497}; 498 499extern struct of_device_id __clk_of_table; 500 501#define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn) 502 503#ifdef CONFIG_OF 504int of_clk_add_provider(struct device_node *np, 505 struct clk *(*clk_src_get)(struct of_phandle_args *args, 506 void *data), 507 void *data); 508void of_clk_del_provider(struct device_node *np); 509struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 510 void *data); 511struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 512int of_clk_get_parent_count(struct device_node *np); 513const char *of_clk_get_parent_name(struct device_node *np, int index); 514 515void of_clk_init(const struct of_device_id *matches); 516 517#else /* !CONFIG_OF */ 518 519static inline int of_clk_add_provider(struct device_node *np, 520 struct clk *(*clk_src_get)(struct of_phandle_args *args, 521 void *data), 522 void *data) 523{ 524 return 0; 525} 526#define of_clk_del_provider(np) \ 527 { while (0); } 528static inline struct clk *of_clk_src_simple_get( 529 struct of_phandle_args *clkspec, void *data) 530{ 531 return ERR_PTR(-ENOENT); 532} 533static inline struct clk *of_clk_src_onecell_get( 534 struct of_phandle_args *clkspec, void *data) 535{ 536 return ERR_PTR(-ENOENT); 537} 538static inline const char *of_clk_get_parent_name(struct device_node *np, 539 int index) 540{ 541 return NULL; 542} 543#define of_clk_init(matches) \ 544 { while (0); } 545#endif /* CONFIG_OF */ 546 547/* 548 * wrap access to peripherals in accessor routines 549 * for improved portability across platforms 550 */ 551 552#if IS_ENABLED(CONFIG_PPC) 553 554static inline u32 clk_readl(u32 __iomem *reg) 555{ 556 return ioread32be(reg); 557} 558 559static inline void clk_writel(u32 val, u32 __iomem *reg) 560{ 561 iowrite32be(val, reg); 562} 563 564#else /* platform dependent I/O accessors */ 565 566static inline u32 clk_readl(u32 __iomem *reg) 567{ 568 return readl(reg); 569} 570 571static inline void clk_writel(u32 val, u32 __iomem *reg) 572{ 573 writel(val, reg); 574} 575 576#endif /* platform dependent I/O accessors */ 577 578#endif /* CONFIG_COMMON_CLK */ 579#endif /* CLK_PROVIDER_H */ 580