clk-provider.h revision 819c1de344c5b8350bffd35be9a0fa74541292d3
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15 16#ifdef CONFIG_COMMON_CLK 17 18/* 19 * flags used across common struct clk. these flags should only affect the 20 * top-level framework. custom flags for dealing with hardware specifics 21 * belong in struct clk_foo 22 */ 23#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 24#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 25#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 26#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 28#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 29#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 30#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ 31 32struct clk_hw; 33 34/** 35 * struct clk_ops - Callback operations for hardware clocks; these are to 36 * be provided by the clock implementation, and will be called by drivers 37 * through the clk_* api. 38 * 39 * @prepare: Prepare the clock for enabling. This must not return until 40 * the clock is fully prepared, and it's safe to call clk_enable. 41 * This callback is intended to allow clock implementations to 42 * do any initialisation that may sleep. Called with 43 * prepare_lock held. 44 * 45 * @unprepare: Release the clock from its prepared state. This will typically 46 * undo any work done in the @prepare callback. Called with 47 * prepare_lock held. 48 * 49 * @is_prepared: Queries the hardware to determine if the clock is prepared. 50 * This function is allowed to sleep. Optional, if this op is not 51 * set then the prepare count will be used. 52 * 53 * @unprepare_unused: Unprepare the clock atomically. Only called from 54 * clk_disable_unused for prepare clocks with special needs. 55 * Called with prepare mutex held. This function may sleep. 56 * 57 * @enable: Enable the clock atomically. This must not return until the 58 * clock is generating a valid clock signal, usable by consumer 59 * devices. Called with enable_lock held. This function must not 60 * sleep. 61 * 62 * @disable: Disable the clock atomically. Called with enable_lock held. 63 * This function must not sleep. 64 * 65 * @is_enabled: Queries the hardware to determine if the clock is enabled. 66 * This function must not sleep. Optional, if this op is not 67 * set then the enable count will be used. 68 * 69 * @disable_unused: Disable the clock atomically. Only called from 70 * clk_disable_unused for gate clocks with special needs. 71 * Called with enable_lock held. This function must not 72 * sleep. 73 * 74 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The 75 * parent rate is an input parameter. It is up to the caller to 76 * ensure that the prepare_mutex is held across this call. 77 * Returns the calculated rate. Optional, but recommended - if 78 * this op is not set then clock rate will be initialized to 0. 79 * 80 * @round_rate: Given a target rate as input, returns the closest rate actually 81 * supported by the clock. 82 * 83 * @determine_rate: Given a target rate as input, returns the closest rate 84 * actually supported by the clock, and optionally the parent clock 85 * that should be used to provide the clock rate. 86 * 87 * @get_parent: Queries the hardware to determine the parent of a clock. The 88 * return value is a u8 which specifies the index corresponding to 89 * the parent clock. This index can be applied to either the 90 * .parent_names or .parents arrays. In short, this function 91 * translates the parent value read from hardware into an array 92 * index. Currently only called when the clock is initialized by 93 * __clk_init. This callback is mandatory for clocks with 94 * multiple parents. It is optional (and unnecessary) for clocks 95 * with 0 or 1 parents. 96 * 97 * @set_parent: Change the input source of this clock; for clocks with multiple 98 * possible parents specify a new parent by passing in the index 99 * as a u8 corresponding to the parent in either the .parent_names 100 * or .parents arrays. This function in affect translates an 101 * array index into the value programmed into the hardware. 102 * Returns 0 on success, -EERROR otherwise. 103 * 104 * @set_rate: Change the rate of this clock. The requested rate is specified 105 * by the second argument, which should typically be the return 106 * of .round_rate call. The third argument gives the parent rate 107 * which is likely helpful for most .set_rate implementation. 108 * Returns 0 on success, -EERROR otherwise. 109 * 110 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 111 * implementations to split any work between atomic (enable) and sleepable 112 * (prepare) contexts. If enabling a clock requires code that might sleep, 113 * this must be done in clk_prepare. Clock enable code that will never be 114 * called in a sleepable context may be implemented in clk_enable. 115 * 116 * Typically, drivers will call clk_prepare when a clock may be needed later 117 * (eg. when a device is opened), and clk_enable when the clock is actually 118 * required (eg. from an interrupt). Note that clk_prepare MUST have been 119 * called before clk_enable. 120 */ 121struct clk_ops { 122 int (*prepare)(struct clk_hw *hw); 123 void (*unprepare)(struct clk_hw *hw); 124 int (*is_prepared)(struct clk_hw *hw); 125 void (*unprepare_unused)(struct clk_hw *hw); 126 int (*enable)(struct clk_hw *hw); 127 void (*disable)(struct clk_hw *hw); 128 int (*is_enabled)(struct clk_hw *hw); 129 void (*disable_unused)(struct clk_hw *hw); 130 unsigned long (*recalc_rate)(struct clk_hw *hw, 131 unsigned long parent_rate); 132 long (*round_rate)(struct clk_hw *hw, unsigned long, 133 unsigned long *); 134 long (*determine_rate)(struct clk_hw *hw, unsigned long rate, 135 unsigned long *best_parent_rate, 136 struct clk **best_parent_clk); 137 int (*set_parent)(struct clk_hw *hw, u8 index); 138 u8 (*get_parent)(struct clk_hw *hw); 139 int (*set_rate)(struct clk_hw *hw, unsigned long, 140 unsigned long); 141 void (*init)(struct clk_hw *hw); 142}; 143 144/** 145 * struct clk_init_data - holds init data that's common to all clocks and is 146 * shared between the clock provider and the common clock framework. 147 * 148 * @name: clock name 149 * @ops: operations this clock supports 150 * @parent_names: array of string names for all possible parents 151 * @num_parents: number of possible parents 152 * @flags: framework-level hints and quirks 153 */ 154struct clk_init_data { 155 const char *name; 156 const struct clk_ops *ops; 157 const char **parent_names; 158 u8 num_parents; 159 unsigned long flags; 160}; 161 162/** 163 * struct clk_hw - handle for traversing from a struct clk to its corresponding 164 * hardware-specific structure. struct clk_hw should be declared within struct 165 * clk_foo and then referenced by the struct clk instance that uses struct 166 * clk_foo's clk_ops 167 * 168 * @clk: pointer to the struct clk instance that points back to this struct 169 * clk_hw instance 170 * 171 * @init: pointer to struct clk_init_data that contains the init data shared 172 * with the common clock framework. 173 */ 174struct clk_hw { 175 struct clk *clk; 176 const struct clk_init_data *init; 177}; 178 179/* 180 * DOC: Basic clock implementations common to many platforms 181 * 182 * Each basic clock hardware type is comprised of a structure describing the 183 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 184 * unique flags for that hardware type, a registration function and an 185 * alternative macro for static initialization 186 */ 187 188/** 189 * struct clk_fixed_rate - fixed-rate clock 190 * @hw: handle between common and hardware-specific interfaces 191 * @fixed_rate: constant frequency of clock 192 */ 193struct clk_fixed_rate { 194 struct clk_hw hw; 195 unsigned long fixed_rate; 196 u8 flags; 197}; 198 199extern const struct clk_ops clk_fixed_rate_ops; 200struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 201 const char *parent_name, unsigned long flags, 202 unsigned long fixed_rate); 203 204void of_fixed_clk_setup(struct device_node *np); 205 206/** 207 * struct clk_gate - gating clock 208 * 209 * @hw: handle between common and hardware-specific interfaces 210 * @reg: register controlling gate 211 * @bit_idx: single bit controlling gate 212 * @flags: hardware-specific flags 213 * @lock: register lock 214 * 215 * Clock which can gate its output. Implements .enable & .disable 216 * 217 * Flags: 218 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 219 * enable the clock. Setting this flag does the opposite: setting the bit 220 * disable the clock and clearing it enables the clock 221 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit 222 * of this register, and mask of gate bits are in higher 16-bit of this 223 * register. While setting the gate bits, higher 16-bit should also be 224 * updated to indicate changing gate bits. 225 */ 226struct clk_gate { 227 struct clk_hw hw; 228 void __iomem *reg; 229 u8 bit_idx; 230 u8 flags; 231 spinlock_t *lock; 232}; 233 234#define CLK_GATE_SET_TO_DISABLE BIT(0) 235#define CLK_GATE_HIWORD_MASK BIT(1) 236 237extern const struct clk_ops clk_gate_ops; 238struct clk *clk_register_gate(struct device *dev, const char *name, 239 const char *parent_name, unsigned long flags, 240 void __iomem *reg, u8 bit_idx, 241 u8 clk_gate_flags, spinlock_t *lock); 242 243struct clk_div_table { 244 unsigned int val; 245 unsigned int div; 246}; 247 248/** 249 * struct clk_divider - adjustable divider clock 250 * 251 * @hw: handle between common and hardware-specific interfaces 252 * @reg: register containing the divider 253 * @shift: shift to the divider bit field 254 * @width: width of the divider bit field 255 * @table: array of value/divider pairs, last entry should have div = 0 256 * @lock: register lock 257 * 258 * Clock with an adjustable divider affecting its output frequency. Implements 259 * .recalc_rate, .set_rate and .round_rate 260 * 261 * Flags: 262 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 263 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 264 * the raw value read from the register, with the value of zero considered 265 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. 266 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 267 * the hardware register 268 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have 269 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. 270 * Some hardware implementations gracefully handle this case and allow a 271 * zero divisor by not modifying their input clock 272 * (divide by one / bypass). 273 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit 274 * of this register, and mask of divider bits are in higher 16-bit of this 275 * register. While setting the divider bits, higher 16-bit should also be 276 * updated to indicate changing divider bits. 277 */ 278struct clk_divider { 279 struct clk_hw hw; 280 void __iomem *reg; 281 u8 shift; 282 u8 width; 283 u8 flags; 284 const struct clk_div_table *table; 285 spinlock_t *lock; 286}; 287 288#define CLK_DIVIDER_ONE_BASED BIT(0) 289#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 290#define CLK_DIVIDER_ALLOW_ZERO BIT(2) 291#define CLK_DIVIDER_HIWORD_MASK BIT(3) 292 293extern const struct clk_ops clk_divider_ops; 294struct clk *clk_register_divider(struct device *dev, const char *name, 295 const char *parent_name, unsigned long flags, 296 void __iomem *reg, u8 shift, u8 width, 297 u8 clk_divider_flags, spinlock_t *lock); 298struct clk *clk_register_divider_table(struct device *dev, const char *name, 299 const char *parent_name, unsigned long flags, 300 void __iomem *reg, u8 shift, u8 width, 301 u8 clk_divider_flags, const struct clk_div_table *table, 302 spinlock_t *lock); 303 304/** 305 * struct clk_mux - multiplexer clock 306 * 307 * @hw: handle between common and hardware-specific interfaces 308 * @reg: register controlling multiplexer 309 * @shift: shift to multiplexer bit field 310 * @width: width of mutliplexer bit field 311 * @flags: hardware-specific flags 312 * @lock: register lock 313 * 314 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 315 * and .recalc_rate 316 * 317 * Flags: 318 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 319 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 320 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 321 * register, and mask of mux bits are in higher 16-bit of this register. 322 * While setting the mux bits, higher 16-bit should also be updated to 323 * indicate changing mux bits. 324 */ 325struct clk_mux { 326 struct clk_hw hw; 327 void __iomem *reg; 328 u32 *table; 329 u32 mask; 330 u8 shift; 331 u8 flags; 332 spinlock_t *lock; 333}; 334 335#define CLK_MUX_INDEX_ONE BIT(0) 336#define CLK_MUX_INDEX_BIT BIT(1) 337#define CLK_MUX_HIWORD_MASK BIT(2) 338#define CLK_MUX_READ_ONLY BIT(3) /* mux setting cannot be changed */ 339 340extern const struct clk_ops clk_mux_ops; 341extern const struct clk_ops clk_mux_ro_ops; 342 343struct clk *clk_register_mux(struct device *dev, const char *name, 344 const char **parent_names, u8 num_parents, unsigned long flags, 345 void __iomem *reg, u8 shift, u8 width, 346 u8 clk_mux_flags, spinlock_t *lock); 347 348struct clk *clk_register_mux_table(struct device *dev, const char *name, 349 const char **parent_names, u8 num_parents, unsigned long flags, 350 void __iomem *reg, u8 shift, u32 mask, 351 u8 clk_mux_flags, u32 *table, spinlock_t *lock); 352 353void of_fixed_factor_clk_setup(struct device_node *node); 354 355/** 356 * struct clk_fixed_factor - fixed multiplier and divider clock 357 * 358 * @hw: handle between common and hardware-specific interfaces 359 * @mult: multiplier 360 * @div: divider 361 * 362 * Clock with a fixed multiplier and divider. The output frequency is the 363 * parent clock rate divided by div and multiplied by mult. 364 * Implements .recalc_rate, .set_rate and .round_rate 365 */ 366 367struct clk_fixed_factor { 368 struct clk_hw hw; 369 unsigned int mult; 370 unsigned int div; 371}; 372 373extern struct clk_ops clk_fixed_factor_ops; 374struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 375 const char *parent_name, unsigned long flags, 376 unsigned int mult, unsigned int div); 377 378/*** 379 * struct clk_composite - aggregate clock of mux, divider and gate clocks 380 * 381 * @hw: handle between common and hardware-specific interfaces 382 * @mux_hw: handle between composite and hardware-specific mux clock 383 * @rate_hw: handle between composite and hardware-specific rate clock 384 * @gate_hw: handle between composite and hardware-specific gate clock 385 * @mux_ops: clock ops for mux 386 * @rate_ops: clock ops for rate 387 * @gate_ops: clock ops for gate 388 */ 389struct clk_composite { 390 struct clk_hw hw; 391 struct clk_ops ops; 392 393 struct clk_hw *mux_hw; 394 struct clk_hw *rate_hw; 395 struct clk_hw *gate_hw; 396 397 const struct clk_ops *mux_ops; 398 const struct clk_ops *rate_ops; 399 const struct clk_ops *gate_ops; 400}; 401 402struct clk *clk_register_composite(struct device *dev, const char *name, 403 const char **parent_names, int num_parents, 404 struct clk_hw *mux_hw, const struct clk_ops *mux_ops, 405 struct clk_hw *rate_hw, const struct clk_ops *rate_ops, 406 struct clk_hw *gate_hw, const struct clk_ops *gate_ops, 407 unsigned long flags); 408 409/** 410 * clk_register - allocate a new clock, register it and return an opaque cookie 411 * @dev: device that is registering this clock 412 * @hw: link to hardware-specific clock data 413 * 414 * clk_register is the primary interface for populating the clock tree with new 415 * clock nodes. It returns a pointer to the newly allocated struct clk which 416 * cannot be dereferenced by driver code but may be used in conjuction with the 417 * rest of the clock API. In the event of an error clk_register will return an 418 * error code; drivers must test for an error code after calling clk_register. 419 */ 420struct clk *clk_register(struct device *dev, struct clk_hw *hw); 421struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); 422 423void clk_unregister(struct clk *clk); 424void devm_clk_unregister(struct device *dev, struct clk *clk); 425 426/* helper functions */ 427const char *__clk_get_name(struct clk *clk); 428struct clk_hw *__clk_get_hw(struct clk *clk); 429u8 __clk_get_num_parents(struct clk *clk); 430struct clk *__clk_get_parent(struct clk *clk); 431struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); 432unsigned int __clk_get_enable_count(struct clk *clk); 433unsigned int __clk_get_prepare_count(struct clk *clk); 434unsigned long __clk_get_rate(struct clk *clk); 435unsigned long __clk_get_flags(struct clk *clk); 436bool __clk_is_prepared(struct clk *clk); 437bool __clk_is_enabled(struct clk *clk); 438struct clk *__clk_lookup(const char *name); 439 440/* 441 * FIXME clock api without lock protection 442 */ 443int __clk_prepare(struct clk *clk); 444void __clk_unprepare(struct clk *clk); 445void __clk_reparent(struct clk *clk, struct clk *new_parent); 446unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 447 448struct of_device_id; 449 450typedef void (*of_clk_init_cb_t)(struct device_node *); 451 452struct clk_onecell_data { 453 struct clk **clks; 454 unsigned int clk_num; 455}; 456 457#define CLK_OF_DECLARE(name, compat, fn) \ 458 static const struct of_device_id __clk_of_table_##name \ 459 __used __section(__clk_of_table) \ 460 = { .compatible = compat, .data = fn }; 461 462#ifdef CONFIG_OF 463int of_clk_add_provider(struct device_node *np, 464 struct clk *(*clk_src_get)(struct of_phandle_args *args, 465 void *data), 466 void *data); 467void of_clk_del_provider(struct device_node *np); 468struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 469 void *data); 470struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 471const char *of_clk_get_parent_name(struct device_node *np, int index); 472 473void of_clk_init(const struct of_device_id *matches); 474 475#else /* !CONFIG_OF */ 476 477static inline int of_clk_add_provider(struct device_node *np, 478 struct clk *(*clk_src_get)(struct of_phandle_args *args, 479 void *data), 480 void *data) 481{ 482 return 0; 483} 484#define of_clk_del_provider(np) \ 485 { while (0); } 486static inline struct clk *of_clk_src_simple_get( 487 struct of_phandle_args *clkspec, void *data) 488{ 489 return ERR_PTR(-ENOENT); 490} 491static inline struct clk *of_clk_src_onecell_get( 492 struct of_phandle_args *clkspec, void *data) 493{ 494 return ERR_PTR(-ENOENT); 495} 496static inline const char *of_clk_get_parent_name(struct device_node *np, 497 int index) 498{ 499 return NULL; 500} 501#define of_clk_init(matches) \ 502 { while (0); } 503#endif /* CONFIG_OF */ 504#endif /* CONFIG_COMMON_CLK */ 505#endif /* CLK_PROVIDER_H */ 506