clk-provider.h revision a093bde2b45a0a745f12c018e2d13c027d58641f
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15 16#ifdef CONFIG_COMMON_CLK 17 18/* 19 * flags used across common struct clk. these flags should only affect the 20 * top-level framework. custom flags for dealing with hardware specifics 21 * belong in struct clk_foo 22 */ 23#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 24#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 25#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 26#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 28#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 29#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 30 31struct clk_hw; 32 33/** 34 * struct clk_ops - Callback operations for hardware clocks; these are to 35 * be provided by the clock implementation, and will be called by drivers 36 * through the clk_* api. 37 * 38 * @prepare: Prepare the clock for enabling. This must not return until 39 * the clock is fully prepared, and it's safe to call clk_enable. 40 * This callback is intended to allow clock implementations to 41 * do any initialisation that may sleep. Called with 42 * prepare_lock held. 43 * 44 * @unprepare: Release the clock from its prepared state. This will typically 45 * undo any work done in the @prepare callback. Called with 46 * prepare_lock held. 47 * 48 * @enable: Enable the clock atomically. This must not return until the 49 * clock is generating a valid clock signal, usable by consumer 50 * devices. Called with enable_lock held. This function must not 51 * sleep. 52 * 53 * @disable: Disable the clock atomically. Called with enable_lock held. 54 * This function must not sleep. 55 * 56 * @recalc_rate Recalculate the rate of this clock, by quering hardware. The 57 * parent rate is an input parameter. It is up to the caller to 58 * insure that the prepare_mutex is held across this call. 59 * Returns the calculated rate. Optional, but recommended - if 60 * this op is not set then clock rate will be initialized to 0. 61 * 62 * @round_rate: Given a target rate as input, returns the closest rate actually 63 * supported by the clock. 64 * 65 * @get_parent: Queries the hardware to determine the parent of a clock. The 66 * return value is a u8 which specifies the index corresponding to 67 * the parent clock. This index can be applied to either the 68 * .parent_names or .parents arrays. In short, this function 69 * translates the parent value read from hardware into an array 70 * index. Currently only called when the clock is initialized by 71 * __clk_init. This callback is mandatory for clocks with 72 * multiple parents. It is optional (and unnecessary) for clocks 73 * with 0 or 1 parents. 74 * 75 * @set_parent: Change the input source of this clock; for clocks with multiple 76 * possible parents specify a new parent by passing in the index 77 * as a u8 corresponding to the parent in either the .parent_names 78 * or .parents arrays. This function in affect translates an 79 * array index into the value programmed into the hardware. 80 * Returns 0 on success, -EERROR otherwise. 81 * 82 * @set_rate: Change the rate of this clock. The requested rate is specified 83 * by the second argument, which should typically be the return 84 * of .round_rate call. The third argument gives the parent rate 85 * which is likely helpful for most .set_rate implementation. 86 * Returns 0 on success, -EERROR otherwise. 87 * 88 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 89 * implementations to split any work between atomic (enable) and sleepable 90 * (prepare) contexts. If enabling a clock requires code that might sleep, 91 * this must be done in clk_prepare. Clock enable code that will never be 92 * called in a sleepable context may be implement in clk_enable. 93 * 94 * Typically, drivers will call clk_prepare when a clock may be needed later 95 * (eg. when a device is opened), and clk_enable when the clock is actually 96 * required (eg. from an interrupt). Note that clk_prepare MUST have been 97 * called before clk_enable. 98 */ 99struct clk_ops { 100 int (*prepare)(struct clk_hw *hw); 101 void (*unprepare)(struct clk_hw *hw); 102 int (*enable)(struct clk_hw *hw); 103 void (*disable)(struct clk_hw *hw); 104 int (*is_enabled)(struct clk_hw *hw); 105 unsigned long (*recalc_rate)(struct clk_hw *hw, 106 unsigned long parent_rate); 107 long (*round_rate)(struct clk_hw *hw, unsigned long, 108 unsigned long *); 109 int (*set_parent)(struct clk_hw *hw, u8 index); 110 u8 (*get_parent)(struct clk_hw *hw); 111 int (*set_rate)(struct clk_hw *hw, unsigned long, 112 unsigned long); 113 void (*init)(struct clk_hw *hw); 114}; 115 116/** 117 * struct clk_init_data - holds init data that's common to all clocks and is 118 * shared between the clock provider and the common clock framework. 119 * 120 * @name: clock name 121 * @ops: operations this clock supports 122 * @parent_names: array of string names for all possible parents 123 * @num_parents: number of possible parents 124 * @flags: framework-level hints and quirks 125 */ 126struct clk_init_data { 127 const char *name; 128 const struct clk_ops *ops; 129 const char **parent_names; 130 u8 num_parents; 131 unsigned long flags; 132}; 133 134/** 135 * struct clk_hw - handle for traversing from a struct clk to its corresponding 136 * hardware-specific structure. struct clk_hw should be declared within struct 137 * clk_foo and then referenced by the struct clk instance that uses struct 138 * clk_foo's clk_ops 139 * 140 * @clk: pointer to the struct clk instance that points back to this struct 141 * clk_hw instance 142 * 143 * @init: pointer to struct clk_init_data that contains the init data shared 144 * with the common clock framework. 145 */ 146struct clk_hw { 147 struct clk *clk; 148 const struct clk_init_data *init; 149}; 150 151/* 152 * DOC: Basic clock implementations common to many platforms 153 * 154 * Each basic clock hardware type is comprised of a structure describing the 155 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 156 * unique flags for that hardware type, a registration function and an 157 * alternative macro for static initialization 158 */ 159 160/** 161 * struct clk_fixed_rate - fixed-rate clock 162 * @hw: handle between common and hardware-specific interfaces 163 * @fixed_rate: constant frequency of clock 164 */ 165struct clk_fixed_rate { 166 struct clk_hw hw; 167 unsigned long fixed_rate; 168 u8 flags; 169}; 170 171extern const struct clk_ops clk_fixed_rate_ops; 172struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 173 const char *parent_name, unsigned long flags, 174 unsigned long fixed_rate); 175 176void of_fixed_clk_setup(struct device_node *np); 177 178/** 179 * struct clk_gate - gating clock 180 * 181 * @hw: handle between common and hardware-specific interfaces 182 * @reg: register controlling gate 183 * @bit_idx: single bit controlling gate 184 * @flags: hardware-specific flags 185 * @lock: register lock 186 * 187 * Clock which can gate its output. Implements .enable & .disable 188 * 189 * Flags: 190 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to 191 * enable the clock. Setting this flag does the opposite: setting the bit 192 * disable the clock and clearing it enables the clock 193 */ 194struct clk_gate { 195 struct clk_hw hw; 196 void __iomem *reg; 197 u8 bit_idx; 198 u8 flags; 199 spinlock_t *lock; 200}; 201 202#define CLK_GATE_SET_TO_DISABLE BIT(0) 203 204extern const struct clk_ops clk_gate_ops; 205struct clk *clk_register_gate(struct device *dev, const char *name, 206 const char *parent_name, unsigned long flags, 207 void __iomem *reg, u8 bit_idx, 208 u8 clk_gate_flags, spinlock_t *lock); 209 210struct clk_div_table { 211 unsigned int val; 212 unsigned int div; 213}; 214 215/** 216 * struct clk_divider - adjustable divider clock 217 * 218 * @hw: handle between common and hardware-specific interfaces 219 * @reg: register containing the divider 220 * @shift: shift to the divider bit field 221 * @width: width of the divider bit field 222 * @table: array of value/divider pairs, last entry should have div = 0 223 * @lock: register lock 224 * 225 * Clock with an adjustable divider affecting its output frequency. Implements 226 * .recalc_rate, .set_rate and .round_rate 227 * 228 * Flags: 229 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 230 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 231 * the raw value read from the register, with the value of zero considered 232 * invalid 233 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 234 * the hardware register 235 */ 236struct clk_divider { 237 struct clk_hw hw; 238 void __iomem *reg; 239 u8 shift; 240 u8 width; 241 u8 flags; 242 const struct clk_div_table *table; 243 spinlock_t *lock; 244}; 245 246#define CLK_DIVIDER_ONE_BASED BIT(0) 247#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 248 249extern const struct clk_ops clk_divider_ops; 250struct clk *clk_register_divider(struct device *dev, const char *name, 251 const char *parent_name, unsigned long flags, 252 void __iomem *reg, u8 shift, u8 width, 253 u8 clk_divider_flags, spinlock_t *lock); 254struct clk *clk_register_divider_table(struct device *dev, const char *name, 255 const char *parent_name, unsigned long flags, 256 void __iomem *reg, u8 shift, u8 width, 257 u8 clk_divider_flags, const struct clk_div_table *table, 258 spinlock_t *lock); 259 260/** 261 * struct clk_mux - multiplexer clock 262 * 263 * @hw: handle between common and hardware-specific interfaces 264 * @reg: register controlling multiplexer 265 * @shift: shift to multiplexer bit field 266 * @width: width of mutliplexer bit field 267 * @num_clks: number of parent clocks 268 * @lock: register lock 269 * 270 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 271 * and .recalc_rate 272 * 273 * Flags: 274 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 275 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) 276 */ 277struct clk_mux { 278 struct clk_hw hw; 279 void __iomem *reg; 280 u8 shift; 281 u8 width; 282 u8 flags; 283 spinlock_t *lock; 284}; 285 286#define CLK_MUX_INDEX_ONE BIT(0) 287#define CLK_MUX_INDEX_BIT BIT(1) 288 289extern const struct clk_ops clk_mux_ops; 290struct clk *clk_register_mux(struct device *dev, const char *name, 291 const char **parent_names, u8 num_parents, unsigned long flags, 292 void __iomem *reg, u8 shift, u8 width, 293 u8 clk_mux_flags, spinlock_t *lock); 294 295/** 296 * struct clk_fixed_factor - fixed multiplier and divider clock 297 * 298 * @hw: handle between common and hardware-specific interfaces 299 * @mult: multiplier 300 * @div: divider 301 * 302 * Clock with a fixed multiplier and divider. The output frequency is the 303 * parent clock rate divided by div and multiplied by mult. 304 * Implements .recalc_rate, .set_rate and .round_rate 305 */ 306 307struct clk_fixed_factor { 308 struct clk_hw hw; 309 unsigned int mult; 310 unsigned int div; 311}; 312 313extern struct clk_ops clk_fixed_factor_ops; 314struct clk *clk_register_fixed_factor(struct device *dev, const char *name, 315 const char *parent_name, unsigned long flags, 316 unsigned int mult, unsigned int div); 317 318/** 319 * clk_register - allocate a new clock, register it and return an opaque cookie 320 * @dev: device that is registering this clock 321 * @hw: link to hardware-specific clock data 322 * 323 * clk_register is the primary interface for populating the clock tree with new 324 * clock nodes. It returns a pointer to the newly allocated struct clk which 325 * cannot be dereferenced by driver code but may be used in conjuction with the 326 * rest of the clock API. In the event of an error clk_register will return an 327 * error code; drivers must test for an error code after calling clk_register. 328 */ 329struct clk *clk_register(struct device *dev, struct clk_hw *hw); 330 331void clk_unregister(struct clk *clk); 332 333/* helper functions */ 334const char *__clk_get_name(struct clk *clk); 335struct clk_hw *__clk_get_hw(struct clk *clk); 336u8 __clk_get_num_parents(struct clk *clk); 337struct clk *__clk_get_parent(struct clk *clk); 338inline int __clk_get_enable_count(struct clk *clk); 339inline int __clk_get_prepare_count(struct clk *clk); 340unsigned long __clk_get_rate(struct clk *clk); 341unsigned long __clk_get_flags(struct clk *clk); 342int __clk_is_enabled(struct clk *clk); 343struct clk *__clk_lookup(const char *name); 344 345/* 346 * FIXME clock api without lock protection 347 */ 348int __clk_prepare(struct clk *clk); 349void __clk_unprepare(struct clk *clk); 350void __clk_reparent(struct clk *clk, struct clk *new_parent); 351unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 352 353struct of_device_id; 354 355typedef void (*of_clk_init_cb_t)(struct device_node *); 356 357int of_clk_add_provider(struct device_node *np, 358 struct clk *(*clk_src_get)(struct of_phandle_args *args, 359 void *data), 360 void *data); 361void of_clk_del_provider(struct device_node *np); 362struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 363 void *data); 364const char *of_clk_get_parent_name(struct device_node *np, int index); 365void of_clk_init(const struct of_device_id *matches); 366 367#endif /* CONFIG_COMMON_CLK */ 368#endif /* CLK_PROVIDER_H */ 369