clk-provider.h revision bffad66e31fe9d94cd096f2e4de7c683e1ae32ef
1/* 2 * linux/include/linux/clk-provider.h 3 * 4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> 5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#ifndef __LINUX_CLK_PROVIDER_H 12#define __LINUX_CLK_PROVIDER_H 13 14#include <linux/clk.h> 15 16#ifdef CONFIG_COMMON_CLK 17 18/** 19 * struct clk_hw - handle for traversing from a struct clk to its corresponding 20 * hardware-specific structure. struct clk_hw should be declared within struct 21 * clk_foo and then referenced by the struct clk instance that uses struct 22 * clk_foo's clk_ops 23 * 24 * clk: pointer to the struct clk instance that points back to this struct 25 * clk_hw instance 26 */ 27struct clk_hw { 28 struct clk *clk; 29}; 30 31/* 32 * flags used across common struct clk. these flags should only affect the 33 * top-level framework. custom flags for dealing with hardware specifics 34 * belong in struct clk_foo 35 */ 36#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ 37#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ 38#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ 39#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 40#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 41 42/** 43 * struct clk_ops - Callback operations for hardware clocks; these are to 44 * be provided by the clock implementation, and will be called by drivers 45 * through the clk_* api. 46 * 47 * @prepare: Prepare the clock for enabling. This must not return until 48 * the clock is fully prepared, and it's safe to call clk_enable. 49 * This callback is intended to allow clock implementations to 50 * do any initialisation that may sleep. Called with 51 * prepare_lock held. 52 * 53 * @unprepare: Release the clock from its prepared state. This will typically 54 * undo any work done in the @prepare callback. Called with 55 * prepare_lock held. 56 * 57 * @enable: Enable the clock atomically. This must not return until the 58 * clock is generating a valid clock signal, usable by consumer 59 * devices. Called with enable_lock held. This function must not 60 * sleep. 61 * 62 * @disable: Disable the clock atomically. Called with enable_lock held. 63 * This function must not sleep. 64 * 65 * @recalc_rate Recalculate the rate of this clock, by quering hardware. The 66 * parent rate is an input parameter. It is up to the caller to 67 * insure that the prepare_mutex is held across this call. 68 * Returns the calculated rate. Optional, but recommended - if 69 * this op is not set then clock rate will be initialized to 0. 70 * 71 * @round_rate: Given a target rate as input, returns the closest rate actually 72 * supported by the clock. 73 * 74 * @get_parent: Queries the hardware to determine the parent of a clock. The 75 * return value is a u8 which specifies the index corresponding to 76 * the parent clock. This index can be applied to either the 77 * .parent_names or .parents arrays. In short, this function 78 * translates the parent value read from hardware into an array 79 * index. Currently only called when the clock is initialized by 80 * __clk_init. This callback is mandatory for clocks with 81 * multiple parents. It is optional (and unnecessary) for clocks 82 * with 0 or 1 parents. 83 * 84 * @set_parent: Change the input source of this clock; for clocks with multiple 85 * possible parents specify a new parent by passing in the index 86 * as a u8 corresponding to the parent in either the .parent_names 87 * or .parents arrays. This function in affect translates an 88 * array index into the value programmed into the hardware. 89 * Returns 0 on success, -EERROR otherwise. 90 * 91 * @set_rate: Change the rate of this clock. If this callback returns 92 * CLK_SET_RATE_PARENT, the rate change will be propagated to the 93 * parent clock (which may propagate again if the parent clock 94 * also sets this flag). The requested rate of the parent is 95 * passed back from the callback in the second 'unsigned long *' 96 * argument. Note that it is up to the hardware clock's set_rate 97 * implementation to insure that clocks do not run out of spec 98 * when propgating the call to set_rate up to the parent. One way 99 * to do this is to gate the clock (via clk_disable and/or 100 * clk_unprepare) before calling clk_set_rate, then ungating it 101 * afterward. If your clock also has the CLK_GATE_SET_RATE flag 102 * set then this will insure safety. Returns 0 on success, 103 * -EERROR otherwise. 104 * 105 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 106 * implementations to split any work between atomic (enable) and sleepable 107 * (prepare) contexts. If enabling a clock requires code that might sleep, 108 * this must be done in clk_prepare. Clock enable code that will never be 109 * called in a sleepable context may be implement in clk_enable. 110 * 111 * Typically, drivers will call clk_prepare when a clock may be needed later 112 * (eg. when a device is opened), and clk_enable when the clock is actually 113 * required (eg. from an interrupt). Note that clk_prepare MUST have been 114 * called before clk_enable. 115 */ 116struct clk_ops { 117 int (*prepare)(struct clk_hw *hw); 118 void (*unprepare)(struct clk_hw *hw); 119 int (*enable)(struct clk_hw *hw); 120 void (*disable)(struct clk_hw *hw); 121 int (*is_enabled)(struct clk_hw *hw); 122 unsigned long (*recalc_rate)(struct clk_hw *hw, 123 unsigned long parent_rate); 124 long (*round_rate)(struct clk_hw *hw, unsigned long, 125 unsigned long *); 126 int (*set_parent)(struct clk_hw *hw, u8 index); 127 u8 (*get_parent)(struct clk_hw *hw); 128 int (*set_rate)(struct clk_hw *hw, unsigned long); 129 void (*init)(struct clk_hw *hw); 130}; 131 132/* 133 * DOC: Basic clock implementations common to many platforms 134 * 135 * Each basic clock hardware type is comprised of a structure describing the 136 * clock hardware, implementations of the relevant callbacks in struct clk_ops, 137 * unique flags for that hardware type, a registration function and an 138 * alternative macro for static initialization 139 */ 140 141/** 142 * struct clk_fixed_rate - fixed-rate clock 143 * @hw: handle between common and hardware-specific interfaces 144 * @fixed_rate: constant frequency of clock 145 */ 146struct clk_fixed_rate { 147 struct clk_hw hw; 148 unsigned long fixed_rate; 149 u8 flags; 150}; 151 152extern const struct clk_ops clk_fixed_rate_ops; 153struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 154 const char *parent_name, unsigned long flags, 155 unsigned long fixed_rate); 156 157/** 158 * struct clk_gate - gating clock 159 * 160 * @hw: handle between common and hardware-specific interfaces 161 * @reg: register controlling gate 162 * @bit_idx: single bit controlling gate 163 * @flags: hardware-specific flags 164 * @lock: register lock 165 * 166 * Clock which can gate its output. Implements .enable & .disable 167 * 168 * Flags: 169 * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to 170 * enable the clock. Setting this flag does the opposite: setting the bit 171 * disable the clock and clearing it enables the clock 172 */ 173struct clk_gate { 174 struct clk_hw hw; 175 void __iomem *reg; 176 u8 bit_idx; 177 u8 flags; 178 spinlock_t *lock; 179 char *parent[1]; 180}; 181 182#define CLK_GATE_SET_TO_DISABLE BIT(0) 183 184extern const struct clk_ops clk_gate_ops; 185struct clk *clk_register_gate(struct device *dev, const char *name, 186 const char *parent_name, unsigned long flags, 187 void __iomem *reg, u8 bit_idx, 188 u8 clk_gate_flags, spinlock_t *lock); 189 190/** 191 * struct clk_divider - adjustable divider clock 192 * 193 * @hw: handle between common and hardware-specific interfaces 194 * @reg: register containing the divider 195 * @shift: shift to the divider bit field 196 * @width: width of the divider bit field 197 * @lock: register lock 198 * 199 * Clock with an adjustable divider affecting its output frequency. Implements 200 * .recalc_rate, .set_rate and .round_rate 201 * 202 * Flags: 203 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the 204 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is 205 * the raw value read from the register, with the value of zero considered 206 * invalid 207 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from 208 * the hardware register 209 */ 210struct clk_divider { 211 struct clk_hw hw; 212 void __iomem *reg; 213 u8 shift; 214 u8 width; 215 u8 flags; 216 spinlock_t *lock; 217 char *parent[1]; 218}; 219 220#define CLK_DIVIDER_ONE_BASED BIT(0) 221#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 222 223extern const struct clk_ops clk_divider_ops; 224struct clk *clk_register_divider(struct device *dev, const char *name, 225 const char *parent_name, unsigned long flags, 226 void __iomem *reg, u8 shift, u8 width, 227 u8 clk_divider_flags, spinlock_t *lock); 228 229/** 230 * struct clk_mux - multiplexer clock 231 * 232 * @hw: handle between common and hardware-specific interfaces 233 * @reg: register controlling multiplexer 234 * @shift: shift to multiplexer bit field 235 * @width: width of mutliplexer bit field 236 * @num_clks: number of parent clocks 237 * @lock: register lock 238 * 239 * Clock with multiple selectable parents. Implements .get_parent, .set_parent 240 * and .recalc_rate 241 * 242 * Flags: 243 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 244 * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two) 245 */ 246struct clk_mux { 247 struct clk_hw hw; 248 void __iomem *reg; 249 u8 shift; 250 u8 width; 251 u8 flags; 252 spinlock_t *lock; 253}; 254 255#define CLK_MUX_INDEX_ONE BIT(0) 256#define CLK_MUX_INDEX_BIT BIT(1) 257 258extern const struct clk_ops clk_mux_ops; 259struct clk *clk_register_mux(struct device *dev, const char *name, 260 char **parent_names, u8 num_parents, unsigned long flags, 261 void __iomem *reg, u8 shift, u8 width, 262 u8 clk_mux_flags, spinlock_t *lock); 263 264/** 265 * clk_register - allocate a new clock, register it and return an opaque cookie 266 * @dev: device that is registering this clock 267 * @name: clock name 268 * @ops: operations this clock supports 269 * @hw: link to hardware-specific clock data 270 * @parent_names: array of string names for all possible parents 271 * @num_parents: number of possible parents 272 * @flags: framework-level hints and quirks 273 * 274 * clk_register is the primary interface for populating the clock tree with new 275 * clock nodes. It returns a pointer to the newly allocated struct clk which 276 * cannot be dereferenced by driver code but may be used in conjuction with the 277 * rest of the clock API. 278 */ 279struct clk *clk_register(struct device *dev, const char *name, 280 const struct clk_ops *ops, struct clk_hw *hw, 281 char **parent_names, u8 num_parents, unsigned long flags); 282 283/* helper functions */ 284const char *__clk_get_name(struct clk *clk); 285struct clk_hw *__clk_get_hw(struct clk *clk); 286u8 __clk_get_num_parents(struct clk *clk); 287struct clk *__clk_get_parent(struct clk *clk); 288inline int __clk_get_enable_count(struct clk *clk); 289inline int __clk_get_prepare_count(struct clk *clk); 290unsigned long __clk_get_rate(struct clk *clk); 291unsigned long __clk_get_flags(struct clk *clk); 292int __clk_is_enabled(struct clk *clk); 293struct clk *__clk_lookup(const char *name); 294 295/* 296 * FIXME clock api without lock protection 297 */ 298int __clk_prepare(struct clk *clk); 299void __clk_unprepare(struct clk *clk); 300void __clk_reparent(struct clk *clk, struct clk *new_parent); 301unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); 302 303#endif /* CONFIG_COMMON_CLK */ 304#endif /* CLK_PROVIDER_H */ 305