145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* 245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang * i2c-bfin-twi.h - interface to ADI TWI controller 345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang * 445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang * Copyright 2005-2014 Analog Devices Inc. 545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang * 645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang * Licensed under the GPL-2 or later. 745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang */ 845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#ifndef __I2C_BFIN_TWI_H__ 1045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define __I2C_BFIN_TWI_H__ 1145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 1245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#include <linux/types.h> 1345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#include <linux/i2c.h> 1445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 1545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* 1645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang * ADI twi registers layout 1745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang */ 1845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhangstruct bfin_twi_regs { 1945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 clkdiv; 2045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy1; 2145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 control; 2245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy2; 2345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 slave_ctl; 2445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy3; 2545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 slave_stat; 2645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy4; 2745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 slave_addr; 2845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy5; 2945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 master_ctl; 3045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy6; 3145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 master_stat; 3245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy7; 3345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 master_addr; 3445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy8; 3545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 int_stat; 3645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy9; 3745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 int_mask; 3845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy10; 3945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 fifo_ctl; 4045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy11; 4145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 fifo_stat; 4245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy12; 4345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u32 __pad[20]; 4445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 xmt_data8; 4545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy13; 4645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 xmt_data16; 4745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy14; 4845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 rcv_data8; 4945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy15; 5045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 rcv_data16; 5145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 dummy16; 5245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang}; 5345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 5445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhangstruct bfin_twi_iface { 5545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang int irq; 5645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang spinlock_t lock; 5745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang char read_write; 5845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u8 command; 5945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u8 *transPtr; 6045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang int readNum; 6145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang int writeNum; 6245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang int cur_mode; 6345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang int manual_stop; 6445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang int result; 6545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang struct i2c_adapter adap; 6645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang struct completion complete; 6745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang struct i2c_msg *pmsg; 6845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang int msg_num; 6945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang int cur_msg; 7045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 saved_clkdiv; 7145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang u16 saved_control; 7245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang struct bfin_twi_regs __iomem *regs_base; 7345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang}; 7445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 7545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/ 7645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */ 7745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */ 7845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */ 7945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 8045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_PRESCALE Masks */ 8145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */ 8245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define TWI_ENA 0x0080 /* TWI Enable */ 8345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SCCB 0x0200 /* SCCB Compatibility Enable */ 8445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 8545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_SLAVE_CTL Masks */ 8645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SEN 0x0001 /* Slave Enable */ 8745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SADD_LEN 0x0002 /* Slave Address Length */ 8845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define STDVAL 0x0004 /* Slave Transmit Data Valid */ 8945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */ 9045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define GEN 0x0010 /* General Call Address Matching Enabled */ 9145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 9245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_SLAVE_STAT Masks */ 9345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */ 9445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define GCALL 0x0002 /* General Call Indicator */ 9545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 9645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_MASTER_CTL Masks */ 9745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define MEN 0x0001 /* Master Mode Enable */ 9845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define MADD_LEN 0x0002 /* Master Address Length */ 9945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */ 10045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define FAST 0x0008 /* Use Fast Mode Timing Specs */ 10145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define STOP 0x0010 /* Issue Stop Condition */ 10245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */ 10345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define DCNT 0x3FC0 /* Data Bytes To Transfer */ 10445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SDAOVR 0x4000 /* Serial Data Override */ 10545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SCLOVR 0x8000 /* Serial Clock Override */ 10645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 10745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_MASTER_STAT Masks */ 10845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define MPROG 0x0001 /* Master Transfer In Progress */ 10945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */ 11045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define ANAK 0x0004 /* Address Not Acknowledged */ 11145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define DNAK 0x0008 /* Data Not Acknowledged */ 11245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define BUFRDERR 0x0010 /* Buffer Read Error */ 11345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define BUFWRERR 0x0020 /* Buffer Write Error */ 11445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SDASEN 0x0040 /* Serial Data Sense */ 11545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SCLSEN 0x0080 /* Serial Clock Sense */ 11645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define BUSBUSY 0x0100 /* Bus Busy Indicator */ 11745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 11845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_INT_SRC and TWI_INT_ENABLE Masks */ 11945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SINIT 0x0001 /* Slave Transfer Initiated */ 12045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SCOMP 0x0002 /* Slave Transfer Complete */ 12145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SERR 0x0004 /* Slave Transfer Error */ 12245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define SOVF 0x0008 /* Slave Overflow */ 12345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define MCOMP 0x0010 /* Master Transfer Complete */ 12445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define MERR 0x0020 /* Master Transfer Error */ 12545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define XMTSERV 0x0040 /* Transmit FIFO Service */ 12645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define RCVSERV 0x0080 /* Receive FIFO Service */ 12745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 12845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_FIFO_CTRL Masks */ 12945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */ 13045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define RCVFLUSH 0x0002 /* Receive Buffer Flush */ 13145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */ 13245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */ 13345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 13445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang/* TWI_FIFO_STAT Masks */ 13545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define XMTSTAT 0x0003 /* Transmit FIFO Status */ 13645126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */ 13745126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */ 13845126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */ 13945126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 14045126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define RCVSTAT 0x000C /* Receive FIFO Status */ 14145126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */ 14245126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */ 14345126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */ 14445126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang 14545126da22452ac3d4685401a1e921a39ac0ff2f6Sonic Zhang#endif 146