16c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* 26c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * incude/mtd/fsmc.h 36c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * 46c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * ST Microelectronics 56c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * Flexible Static Memory Controller (FSMC) 66c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * platform data interface and header file 76c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * 86c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * Copyright © 2010 ST Microelectronics 96c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * Vipin Kumar <vipin.kumar@st.com> 106c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * 116c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * This file is licensed under the terms of the GNU General Public 126c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * License version 2. This program is licensed "as is" without any 136c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * warranty of any kind, whether express or implied. 146c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij */ 156c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 166c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#ifndef __MTD_FSMC_H 176c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define __MTD_FSMC_H 186c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1965ab220c30bc2120eaa39753cadec68616e3f906Viresh Kumar#include <linux/io.h> 206c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <linux/platform_device.h> 216c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <linux/mtd/physmap.h> 226c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <linux/types.h> 236c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <linux/mtd/partitions.h> 246c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <asm/param.h> 256c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 266c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_NAND_BW8 1 276c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_NAND_BW16 2 286c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 296c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_MAX_NOR_BANKS 4 306c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_MAX_NAND_BANKS 4 316c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 326c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_FLASH_WIDTH8 1 336c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_FLASH_WIDTH16 2 346c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 352a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar/* fsmc controller registers for NOR flash */ 362a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define CTRL 0x0 372a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar /* ctrl register definitions */ 382a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define BANK_ENABLE (1 << 0) 392a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define MUXED (1 << 1) 402a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define NOR_DEV (2 << 2) 412a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define WIDTH_8 (0 << 4) 422a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define WIDTH_16 (1 << 4) 432a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define RSTPWRDWN (1 << 6) 442a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define WPROT (1 << 7) 452a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define WRT_ENABLE (1 << 12) 462a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define WAIT_ENB (1 << 13) 472a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar 482a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define CTRL_TIM 0x4 492a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar /* ctrl_tim register definitions */ 502a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar 512a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define FSMC_NOR_BANK_SZ 0x8 526c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_NOR_REG_SIZE 0x40 536c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 542a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define FSMC_NOR_REG(base, bank, reg) (base + \ 552a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar FSMC_NOR_BANK_SZ * (bank) + \ 562a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar reg) 572a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar 582a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar/* fsmc controller registers for NAND flash */ 592a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define PC 0x00 602a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar /* pc register definitions */ 612a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_RESET (1 << 0) 622a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_WAITON (1 << 1) 632a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_ENABLE (1 << 2) 642a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_DEVTYPE_NAND (1 << 3) 652a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_DEVWID_8 (0 << 4) 662a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_DEVWID_16 (1 << 4) 672a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_ECCEN (1 << 6) 682a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_ECCPLEN_512 (0 << 7) 692a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_ECCPLEN_256 (1 << 7) 702a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TCLR_1 (1) 712a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TCLR_SHIFT (9) 722a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TCLR_MASK (0xF) 732a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TAR_1 (1) 742a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TAR_SHIFT (13) 752a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TAR_MASK (0xF) 762a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define STS 0x04 772a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar /* sts register definitions */ 782a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_CODE_RDY (1 << 15) 792a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define COMM 0x08 802a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar /* comm register definitions */ 812a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TSET_0 0 822a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TSET_SHIFT 0 832a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TSET_MASK 0xFF 842a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TWAIT_6 6 852a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TWAIT_SHIFT 8 862a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_TWAIT_MASK 0xFF 872a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_THOLD_4 4 882a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_THOLD_SHIFT 16 892a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_THOLD_MASK 0xFF 902a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_THIZ_1 1 912a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_THIZ_SHIFT 24 922a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar #define FSMC_THIZ_MASK 0xFF 932a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define ATTRIB 0x0C 942a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define IOATA 0x10 952a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define ECC1 0x14 962a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define ECC2 0x18 972a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define ECC3 0x1C 982a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define FSMC_NAND_BANK_SZ 0x20 992a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar 1002a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \ 1012a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar (FSMC_NAND_BANK_SZ * (bank)) + \ 1022a5dbead29a7c081a47133eb428440147a6d8d5aVipin Kumar reg) 1036c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1046c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) 1056c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1066c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* 1076c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 1086c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * and it has to be read consecutively and immediately after the 512 1096c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * byte data block for hardware to generate the error bit offsets 1106c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * Managing the ecc bytes in the following way is easier. This way is 1116c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * similar to oobfree structure maintained already in u-boot nand driver 1126c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij */ 1136c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define MAX_ECCPLACE_ENTRIES 32 1146c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1156c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijstruct fsmc_nand_eccplace { 1166c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint8_t offset; 1176c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint8_t length; 1186c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 1196c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1206c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijstruct fsmc_eccplace { 1216c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES]; 1226c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 1236c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 124e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumarstruct fsmc_nand_timings { 125e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t tclr; 126e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t tar; 127e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t thiz; 128e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t thold; 129e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t twait; 130e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t tset; 131e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar}; 132e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar 133604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumarenum access_mode { 134604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar USE_DMA_ACCESS = 1, 135604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar USE_WORD_ACCESS, 136604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar}; 137604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar 1386c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/** 1396c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * fsmc_nand_platform_data - platform specific NAND controller config 14064ddba4d8a381b65bebee24c8da4eb80080c64a4Mian Yousaf Kaukab * @nand_timings: timing setup for the physical NAND interface 1416c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @partitions: partition table for the platform, use a default fallback 1426c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * if this is NULL 1436c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @nr_partitions: the number of partitions in the previous entry 1446c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @options: different options for the driver 1456c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @width: bus width 1466c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @bank: default bank 1476c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @select_bank: callback to select a certain bank, this is 1486c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * platform-specific. If the controller only supports one bank 1496c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * this may be set to NULL 1506c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij */ 1516c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijstruct fsmc_nand_platform_data { 152e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar struct fsmc_nand_timings *nand_timings; 1536c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij struct mtd_partition *partitions; 1546c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int nr_partitions; 1556c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int options; 1566c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int width; 1576c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int bank; 158b2acc92e144336dd29e30dc5d26439355be750b6Shiraz Hashim 159604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar enum access_mode mode; 160b2acc92e144336dd29e30dc5d26439355be750b6Shiraz Hashim 1616c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij void (*select_bank)(uint32_t bank, uint32_t busw); 1624774fb0a48aacfec206e6d54ecf58706f6a5320aVipin Kumar 1634774fb0a48aacfec206e6d54ecf58706f6a5320aVipin Kumar /* priv structures for dma accesses */ 1644774fb0a48aacfec206e6d54ecf58706f6a5320aVipin Kumar void *read_dma_priv; 1654774fb0a48aacfec206e6d54ecf58706f6a5320aVipin Kumar void *write_dma_priv; 1666c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 1676c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1686c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijextern int __init fsmc_nor_init(struct platform_device *pdev, 1696c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned long base, uint32_t bank, uint32_t width); 1706c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijextern void __init fsmc_init_board_info(struct platform_device *pdev, 1716c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij struct mtd_partition *partitions, unsigned int nr_partitions, 1726c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int width); 1736c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1746c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#endif /* __MTD_FSMC_H */ 175