fsmc.h revision 604e75444fa82cfdcba339e3bd4da1dfd6947539
16c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* 26c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * incude/mtd/fsmc.h 36c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * 46c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * ST Microelectronics 56c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * Flexible Static Memory Controller (FSMC) 66c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * platform data interface and header file 76c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * 86c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * Copyright © 2010 ST Microelectronics 96c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * Vipin Kumar <vipin.kumar@st.com> 106c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * 116c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * This file is licensed under the terms of the GNU General Public 126c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * License version 2. This program is licensed "as is" without any 136c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * warranty of any kind, whether express or implied. 146c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij */ 156c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 166c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#ifndef __MTD_FSMC_H 176c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define __MTD_FSMC_H 186c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1965ab220c30bc2120eaa39753cadec68616e3f906Viresh Kumar#include <linux/io.h> 206c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <linux/platform_device.h> 216c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <linux/mtd/physmap.h> 226c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <linux/types.h> 236c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <linux/mtd/partitions.h> 246c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#include <asm/param.h> 256c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 266c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_NAND_BW8 1 276c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_NAND_BW16 2 286c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 296c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_MAX_NOR_BANKS 4 306c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_MAX_NAND_BANKS 4 316c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 326c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_FLASH_WIDTH8 1 336c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_FLASH_WIDTH16 2 346c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 356c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijstruct fsmc_nor_bank_regs { 366c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t ctrl; 376c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t ctrl_tim; 386c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 396c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 406c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* ctrl register definitions */ 416c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define BANK_ENABLE (1 << 0) 426c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define MUXED (1 << 1) 436c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define NOR_DEV (2 << 2) 446c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define WIDTH_8 (0 << 4) 456c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define WIDTH_16 (1 << 4) 466c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define RSTPWRDWN (1 << 6) 476c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define WPROT (1 << 7) 486c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define WRT_ENABLE (1 << 12) 496c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define WAIT_ENB (1 << 13) 506c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 516c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* ctrl_tim register definitions */ 526c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 53b5602e86432aaf0cc90dd207bf74e3a2bfb5078bLinus Walleijstruct fsmc_nand_bank_regs { 546c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t pc; 556c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t sts; 566c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t comm; 576c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t attrib; 586c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t ioata; 596c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t ecc1; 606c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t ecc2; 616c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t ecc3; 626c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 636c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 646c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_NOR_REG_SIZE 0x40 656c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 666c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijstruct fsmc_regs { 676c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS]; 686c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint8_t reserved_1[0x40 - 0x20]; 69b5602e86432aaf0cc90dd207bf74e3a2bfb5078bLinus Walleij struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS]; 706c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint8_t reserved_2[0xfe0 - 0xc0]; 716c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t peripid0; /* 0xfe0 */ 726c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t peripid1; /* 0xfe4 */ 736c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t peripid2; /* 0xfe8 */ 746c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t peripid3; /* 0xfec */ 756c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t pcellid0; /* 0xff0 */ 766c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t pcellid1; /* 0xff4 */ 776c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t pcellid2; /* 0xff8 */ 786c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint32_t pcellid3; /* 0xffc */ 796c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 806c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 816c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ) 826c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 836c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* pc register definitions */ 846c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_RESET (1 << 0) 856c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_WAITON (1 << 1) 866c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_ENABLE (1 << 2) 876c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_DEVTYPE_NAND (1 << 3) 886c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_DEVWID_8 (0 << 4) 896c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_DEVWID_16 (1 << 4) 906c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_ECCEN (1 << 6) 916c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_ECCPLEN_512 (0 << 7) 926c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_ECCPLEN_256 (1 << 7) 93e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TCLR_1 (1) 94e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TCLR_SHIFT (9) 95e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TCLR_MASK (0xF) 96e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TAR_1 (1) 97e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TAR_SHIFT (13) 98e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TAR_MASK (0xF) 996c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1006c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* sts register definitions */ 1016c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define FSMC_CODE_RDY (1 << 15) 1026c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1036c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* comm register definitions */ 104e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TSET_0 0 105e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TSET_SHIFT 0 106e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TSET_MASK 0xFF 107e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TWAIT_6 6 108e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TWAIT_SHIFT 8 109e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_TWAIT_MASK 0xFF 110e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_THOLD_4 4 111e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_THOLD_SHIFT 16 112e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_THOLD_MASK 0xFF 113e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_THIZ_1 1 114e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_THIZ_SHIFT 24 115e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar#define FSMC_THIZ_MASK 0xFF 1166c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1176c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/* 1186c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * There are 13 bytes of ecc for every 512 byte block in FSMC version 8 1196c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * and it has to be read consecutively and immediately after the 512 1206c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * byte data block for hardware to generate the error bit offsets 1216c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * Managing the ecc bytes in the following way is easier. This way is 1226c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * similar to oobfree structure maintained already in u-boot nand driver 1236c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij */ 1246c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#define MAX_ECCPLACE_ENTRIES 32 1256c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1266c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijstruct fsmc_nand_eccplace { 1276c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint8_t offset; 1286c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij uint8_t length; 1296c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 1306c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1316c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijstruct fsmc_eccplace { 1326c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij struct fsmc_nand_eccplace eccplace[MAX_ECCPLACE_ENTRIES]; 1336c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 1346c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 135e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumarstruct fsmc_nand_timings { 136e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t tclr; 137e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t tar; 138e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t thiz; 139e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t thold; 140e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t twait; 141e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar uint8_t tset; 142e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar}; 143e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar 144604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumarenum access_mode { 145604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar USE_DMA_ACCESS = 1, 146604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar USE_WORD_ACCESS, 147604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar}; 148604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar 1496c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij/** 1506c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * fsmc_nand_platform_data - platform specific NAND controller config 1516c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @partitions: partition table for the platform, use a default fallback 1526c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * if this is NULL 1536c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @nr_partitions: the number of partitions in the previous entry 1546c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @options: different options for the driver 1556c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @width: bus width 1566c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @bank: default bank 1576c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * @select_bank: callback to select a certain bank, this is 1586c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * platform-specific. If the controller only supports one bank 1596c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij * this may be set to NULL 1606c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij */ 1616c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijstruct fsmc_nand_platform_data { 162e2f6bce8d94d2c82d4f7ae9d94743963a3b10136Vipin Kumar struct fsmc_nand_timings *nand_timings; 1636c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij struct mtd_partition *partitions; 1646c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int nr_partitions; 1656c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int options; 1666c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int width; 1676c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int bank; 168b2acc92e144336dd29e30dc5d26439355be750b6Shiraz Hashim 169b2acc92e144336dd29e30dc5d26439355be750b6Shiraz Hashim /* CLE, ALE offsets */ 170b2acc92e144336dd29e30dc5d26439355be750b6Shiraz Hashim unsigned long cle_off; 171b2acc92e144336dd29e30dc5d26439355be750b6Shiraz Hashim unsigned long ale_off; 172604e75444fa82cfdcba339e3bd4da1dfd6947539Vipin Kumar enum access_mode mode; 173b2acc92e144336dd29e30dc5d26439355be750b6Shiraz Hashim 1746c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij void (*select_bank)(uint32_t bank, uint32_t busw); 1756c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij}; 1766c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1776c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijextern int __init fsmc_nor_init(struct platform_device *pdev, 1786c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned long base, uint32_t bank, uint32_t width); 1796c009ab89a212b4364cdb74192d438f542fb291cLinus Walleijextern void __init fsmc_init_board_info(struct platform_device *pdev, 1806c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij struct mtd_partition *partitions, unsigned int nr_partitions, 1816c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij unsigned int width); 1826c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij 1836c009ab89a212b4364cdb74192d438f542fb291cLinus Walleij#endif /* __MTD_FSMC_H */ 184