13bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen/* 2dd5720b3006210ecdf4e3c8889e6051f432c4ba3Andy Shevchenko * Driver for the Synopsys DesignWare DMA Controller 33bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen * 43bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen * Copyright (C) 2007 Atmel Corporation 5aecb7b64dd9e2512c7a4c7e61dd781415d3dac5aViresh Kumar * Copyright (C) 2010-2011 ST Microelectronics 63bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen * 73bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen * This program is free software; you can redistribute it and/or modify 83bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen * it under the terms of the GNU General Public License version 2 as 93bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen * published by the Free Software Foundation. 103bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen */ 113d588f83e4d6a5230d9094b97d38621cbaa9a972Andy Shevchenko#ifndef _PLATFORM_DATA_DMA_DW_H 123d588f83e4d6a5230d9094b97d38621cbaa9a972Andy Shevchenko#define _PLATFORM_DATA_DMA_DW_H 133bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen 143d588f83e4d6a5230d9094b97d38621cbaa9a972Andy Shevchenko#include <linux/device.h> 153bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen 163bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen/** 17a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar * struct dw_dma_slave - Controller-specific information about a slave 18a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar * 19a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar * @dma_dev: required DMA master device. Depricated. 207e1e2f27c5508518e58e5cbb11e26cbb815f4c56Andy Shevchenko * @src_id: src request line 217e1e2f27c5508518e58e5cbb11e26cbb815f4c56Andy Shevchenko * @dst_id: dst request line 22a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar * @src_master: src master for transfers on allocated channel. 23a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar * @dst_master: dest master for transfers on allocated channel. 24a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar */ 25a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumarstruct dw_dma_slave { 26a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar struct device *dma_dev; 277e1e2f27c5508518e58e5cbb11e26cbb815f4c56Andy Shevchenko u8 src_id; 287e1e2f27c5508518e58e5cbb11e26cbb815f4c56Andy Shevchenko u8 dst_id; 29a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar u8 src_master; 30a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar u8 dst_master; 31a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar}; 32a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar 33a9ddb575d6d6c58c39e8c44a22b84445fedb0521Viresh Kumar/** 343bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen * struct dw_dma_platform_data - Controller configuration parameters 353bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen * @nr_channels: Number of channels supported by hardware (max 8) 3695ea759e9e116dade3e7386be2a3db76c90f4675Jamie Iles * @is_private: The device channels should be marked as private and not for 3795ea759e9e116dade3e7386be2a3db76c90f4675Jamie Iles * by the general purpose DMA channel allocator. 38177d2bf5c7d3ab41bfb4ce2597dde668225958ddViresh Kumar * @chan_allocation_order: Allocate channels starting from 0 or 7 39177d2bf5c7d3ab41bfb4ce2597dde668225958ddViresh Kumar * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. 404a63a8b3e8d2e4f56174deb728085010aa3ac2a1Andy Shevchenko * @block_size: Maximum block size supported by the controller 41a09820043c9e11149145a1ec221eed4a7b42dcceAndy Shevchenko * @nr_masters: Number of AHB masters supported by the controller 42a09820043c9e11149145a1ec221eed4a7b42dcceAndy Shevchenko * @data_width: Maximum data width supported by hardware per AHB master 43a09820043c9e11149145a1ec221eed4a7b42dcceAndy Shevchenko * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) 443bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen */ 453bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoenstruct dw_dma_platform_data { 463bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen unsigned int nr_channels; 4795ea759e9e116dade3e7386be2a3db76c90f4675Jamie Iles bool is_private; 48b0c3130d69bda5cd91aa3b3f08e7878df49fde69Viresh Kumar#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 49b0c3130d69bda5cd91aa3b3f08e7878df49fde69Viresh Kumar#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 50b0c3130d69bda5cd91aa3b3f08e7878df49fde69Viresh Kumar unsigned char chan_allocation_order; 5193317e8e35b77633d589fe0e132291195757d785Viresh Kumar#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 5293317e8e35b77633d589fe0e132291195757d785Viresh Kumar#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 5393317e8e35b77633d589fe0e132291195757d785Viresh Kumar unsigned char chan_priority; 544a63a8b3e8d2e4f56174deb728085010aa3ac2a1Andy Shevchenko unsigned short block_size; 55a09820043c9e11149145a1ec221eed4a7b42dcceAndy Shevchenko unsigned char nr_masters; 56a09820043c9e11149145a1ec221eed4a7b42dcceAndy Shevchenko unsigned char data_width[4]; 573bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen}; 583bfb1d20b547a5071d01344581eac5846ea84491Haavard Skinnemoen 593d588f83e4d6a5230d9094b97d38621cbaa9a972Andy Shevchenko#endif /* _PLATFORM_DATA_DMA_DW_H */ 60