pxa2xx_ssp.h revision 25985edcedea6396277003854657b5f3cb31a628
11da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds/* 28348c259dd6a6019a8fa01b0a3443409480f7b9dSebastian Andrzej Siewior * pxa2xx_ssp.h 31da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 41da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * Copyright (C) 2003 Russell King, All Rights Reserved. 51da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 61da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This program is free software; you can redistribute it and/or modify 71da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * it under the terms of the GNU General Public License version 2 as 81da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * published by the Free Software Foundation. 91da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 101da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * This driver supports the following PXA CPU/SSP ports:- 111da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * 121da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PXA250 SSP 131da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PXA255 SSP, NSSP 141da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PXA26x SSP, NSSP, ASSP 151da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds * PXA27x SSP1, SSP2, SSP3 1688286450462216ca9b5c67c2175d75a5aebd5d0feric miao * PXA3xx SSP1, SSP2, SSP3, SSP4 171da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds */ 181da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 198348c259dd6a6019a8fa01b0a3443409480f7b9dSebastian Andrzej Siewior#ifndef __LINUX_SSP_H 208348c259dd6a6019a8fa01b0a3443409480f7b9dSebastian Andrzej Siewior#define __LINUX_SSP_H 2188286450462216ca9b5c67c2175d75a5aebd5d0feric miao 2288286450462216ca9b5c67c2175d75a5aebd5d0feric miao#include <linux/list.h> 2363bef5473892ae683a9e989975180a5754b0ae33Mark Brown#include <linux/io.h> 2488286450462216ca9b5c67c2175d75a5aebd5d0feric miao 2583f2889643d8efbc7fe925afbaa114e775699d7cEric Miao/* 2683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao * SSP Serial Port Registers 2783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different. 2883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao * PXA255, PXA26x and PXA27x have extra ports, registers and bits. 2983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao */ 3083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 3183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0 (0x00) /* SSP Control Register 0 */ 3283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1 (0x04) /* SSP Control Register 1 */ 3383f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR (0x08) /* SSP Status Register */ 3483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSITR (0x0C) /* SSP Interrupt Test Register */ 3583f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSDR (0x10) /* SSP Data Write/Data Read Register */ 3683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 3783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSTO (0x28) /* SSP Time Out Register */ 3883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */ 3983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSTSA (0x30) /* SSP Tx Timeslot Active */ 4083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSRSA (0x34) /* SSP Rx Timeslot Active */ 4183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSTSS (0x38) /* SSP Timeslot Status */ 4283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSACD (0x3C) /* SSP Audio Clock Divider */ 4383f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */ 4483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 4583f2889643d8efbc7fe925afbaa114e775699d7cEric Miao/* Common PXA2xx bits first */ 4683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */ 4783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */ 4883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */ 4983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */ 5083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */ 5183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_National (0x2 << 4) /* National Microwire */ 5283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_ECS (1 << 6) /* External clock select */ 5383f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */ 5483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */ 5583f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 56004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang/* PXA27x, PXA3xx */ 5783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_EDSS (1 << 20) /* Extended data size select */ 5883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_NCS (1 << 21) /* Network clock select */ 5983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ 6083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */ 6183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */ 6283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */ 63004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */ 6483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_ACS (1 << 30) /* Audio clock select */ 6583f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */ 6683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 6783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 6883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */ 6983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */ 7083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */ 7183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */ 7283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */ 7383f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */ 7483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 752a8626a9e2d86d114a2d9f813a1acebf9d53dd10Sebastian Andrzej Siewior#define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */ 7683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */ 7783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */ 7883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_BSY (1 << 4) /* SSP Busy */ 7983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */ 8083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ 8183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ 82d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior 83d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#ifdef CONFIG_ARCH_PXA 84d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define RX_THRESH_DFLT 8 85d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define TX_THRESH_DFLT 8 86d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior 87d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */ 88d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */ 89d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior 90d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */ 91d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */ 92d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ 93d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ 94d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior 95d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#else 96d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior 97d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define RX_THRESH_DFLT 2 98d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define TX_THRESH_DFLT 2 99d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior 100d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */ 101d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */ 102d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior 103d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */ 104d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */ 105d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */ 106d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ 107d0777f2c3eda180e3fc549e0efbe741014f17689Sebastian Andrzej Siewior#endif 10883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 10983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao/* extra bits in PXA255, PXA26x and PXA27x SSP ports */ 11083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */ 11183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */ 11283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */ 11383f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */ 11483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */ 11583f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */ 11683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */ 11783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */ 11883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */ 11983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */ 12083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */ 12183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */ 12283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */ 12383f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ 12483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ 12525985edcedea6396277003854657b5f3cb31a628Lucas De Marchi#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */ 12683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */ 12783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ 12883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ 12983f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 13083f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_BCE (1 << 23) /* Bit Count Error */ 13183f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */ 13283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */ 13383f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_EOC (1 << 20) /* End Of Chain */ 13483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */ 13583f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */ 13683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 13783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 13883f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */ 139004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */ 140004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */ 141004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */ 142004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */ 143004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */ 144004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */ 145004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */ 146004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */ 147004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang 148004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang/* PXA3xx */ 149004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */ 150004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */ 151004690f05244e1a41824cda7dc4feb7804964dc6Haojian Zhuang#define SSPSP_TIMING_MASK (0x7f8001f0) 15283f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 15383f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */ 15483f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */ 15583f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */ 15683f2889643d8efbc7fe925afbaa114e775699d7cEric Miao#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */ 15783f2889643d8efbc7fe925afbaa114e775699d7cEric Miao 15888286450462216ca9b5c67c2175d75a5aebd5d0feric miaoenum pxa_ssp_type { 15988286450462216ca9b5c67c2175d75a5aebd5d0feric miao SSP_UNDEFINED = 0, 16088286450462216ca9b5c67c2175d75a5aebd5d0feric miao PXA25x_SSP, /* pxa 210, 250, 255, 26x */ 16188286450462216ca9b5c67c2175d75a5aebd5d0feric miao PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */ 16288286450462216ca9b5c67c2175d75a5aebd5d0feric miao PXA27x_SSP, 1637e4992288e55f1e15f7498ead618b3943f5cfd3fHaojian Zhuang PXA168_SSP, 1642a8626a9e2d86d114a2d9f813a1acebf9d53dd10Sebastian Andrzej Siewior CE4100_SSP, 16588286450462216ca9b5c67c2175d75a5aebd5d0feric miao}; 16688286450462216ca9b5c67c2175d75a5aebd5d0feric miao 16788286450462216ca9b5c67c2175d75a5aebd5d0feric miaostruct ssp_device { 16888286450462216ca9b5c67c2175d75a5aebd5d0feric miao struct platform_device *pdev; 16988286450462216ca9b5c67c2175d75a5aebd5d0feric miao struct list_head node; 17088286450462216ca9b5c67c2175d75a5aebd5d0feric miao 17188286450462216ca9b5c67c2175d75a5aebd5d0feric miao struct clk *clk; 17288286450462216ca9b5c67c2175d75a5aebd5d0feric miao void __iomem *mmio_base; 17388286450462216ca9b5c67c2175d75a5aebd5d0feric miao unsigned long phys_base; 17488286450462216ca9b5c67c2175d75a5aebd5d0feric miao 17588286450462216ca9b5c67c2175d75a5aebd5d0feric miao const char *label; 17688286450462216ca9b5c67c2175d75a5aebd5d0feric miao int port_id; 17788286450462216ca9b5c67c2175d75a5aebd5d0feric miao int type; 17888286450462216ca9b5c67c2175d75a5aebd5d0feric miao int use_count; 17988286450462216ca9b5c67c2175d75a5aebd5d0feric miao int irq; 18088286450462216ca9b5c67c2175d75a5aebd5d0feric miao int drcmr_rx; 18188286450462216ca9b5c67c2175d75a5aebd5d0feric miao int drcmr_tx; 18288286450462216ca9b5c67c2175d75a5aebd5d0feric miao}; 1831da177e4c3f41524e886b7f1b8a0c1fc7321cacLinus Torvalds 18463bef5473892ae683a9e989975180a5754b0ae33Mark Brown/** 185baffe1699c68da5040de6b274054adc995795782Haojian Zhuang * pxa_ssp_write_reg - Write to a SSP register 18663bef5473892ae683a9e989975180a5754b0ae33Mark Brown * 18763bef5473892ae683a9e989975180a5754b0ae33Mark Brown * @dev: SSP device to access 18863bef5473892ae683a9e989975180a5754b0ae33Mark Brown * @reg: Register to write to 18963bef5473892ae683a9e989975180a5754b0ae33Mark Brown * @val: Value to be written. 19063bef5473892ae683a9e989975180a5754b0ae33Mark Brown */ 191baffe1699c68da5040de6b274054adc995795782Haojian Zhuangstatic inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val) 19263bef5473892ae683a9e989975180a5754b0ae33Mark Brown{ 19363bef5473892ae683a9e989975180a5754b0ae33Mark Brown __raw_writel(val, dev->mmio_base + reg); 19463bef5473892ae683a9e989975180a5754b0ae33Mark Brown} 19563bef5473892ae683a9e989975180a5754b0ae33Mark Brown 19663bef5473892ae683a9e989975180a5754b0ae33Mark Brown/** 197baffe1699c68da5040de6b274054adc995795782Haojian Zhuang * pxa_ssp_read_reg - Read from a SSP register 19863bef5473892ae683a9e989975180a5754b0ae33Mark Brown * 19963bef5473892ae683a9e989975180a5754b0ae33Mark Brown * @dev: SSP device to access 20063bef5473892ae683a9e989975180a5754b0ae33Mark Brown * @reg: Register to read from 20163bef5473892ae683a9e989975180a5754b0ae33Mark Brown */ 202baffe1699c68da5040de6b274054adc995795782Haojian Zhuangstatic inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg) 20363bef5473892ae683a9e989975180a5754b0ae33Mark Brown{ 20463bef5473892ae683a9e989975180a5754b0ae33Mark Brown return __raw_readl(dev->mmio_base + reg); 20563bef5473892ae683a9e989975180a5754b0ae33Mark Brown} 20663bef5473892ae683a9e989975180a5754b0ae33Mark Brown 207baffe1699c68da5040de6b274054adc995795782Haojian Zhuangstruct ssp_device *pxa_ssp_request(int port, const char *label); 208baffe1699c68da5040de6b274054adc995795782Haojian Zhuangvoid pxa_ssp_free(struct ssp_device *); 2098348c259dd6a6019a8fa01b0a3443409480f7b9dSebastian Andrzej Siewior#endif 210