13c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO/******************************************************************************* 23c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 33c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO Header file for stmmac platform data 43c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 53c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO Copyright (C) 2009 STMicroelectronics Ltd 63c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 73c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO This program is free software; you can redistribute it and/or modify it 83c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO under the terms and conditions of the GNU General Public License, 93c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO version 2, as published by the Free Software Foundation. 103c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 113c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO This program is distributed in the hope it will be useful, but WITHOUT 123c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 133c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 143c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO more details. 153c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 163c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO You should have received a copy of the GNU General Public License along with 173c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO this program; if not, write to the Free Software Foundation, Inc., 183c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 193c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 203c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO The full GNU General Public License is included in this distribution in 213c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO the file called "COPYING". 223c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 233c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 243c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO*******************************************************************************/ 253c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 263c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO#ifndef __STMMAC_PLATFORM_DATA 273c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO#define __STMMAC_PLATFORM_DATA 283c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 2957a503c61db077b923e23f36050c02166a4a1db2Viresh Kumar#include <linux/platform_device.h> 3057a503c61db077b923e23f36050c02166a4a1db2Viresh Kumar 3155f9a4d6facb35198ddb88a8fe21ca2ee753af7aDeepak SIKRI#define STMMAC_RX_COE_NONE 0 3255f9a4d6facb35198ddb88a8fe21ca2ee753af7aDeepak SIKRI#define STMMAC_RX_COE_TYPE1 1 3355f9a4d6facb35198ddb88a8fe21ca2ee753af7aDeepak SIKRI#define STMMAC_RX_COE_TYPE2 2 3455f9a4d6facb35198ddb88a8fe21ca2ee753af7aDeepak SIKRI 35faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI/* Define the macros for CSR clock range parameters to be passed by 36faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI * platform code. 37faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI * This could also be configured at run time using CPU freq framework. */ 38faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI 39faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI/* MDC Clock Selection define*/ 4018f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ 4118f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ 4218f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ 4318f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ 4418f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ 4518f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ 46faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI 4718f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO/* The MDC clock could be set higher than the IEEE 802.3 48faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI * specified frequency limit 0f 2.5 MHz, by programming a clock divider 49faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI * of value different than the above defined values. The resultant MDIO 50faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI * clock frequency of 12.5 MHz is applicable for the interfacing chips 51faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI * supporting higher MDC clocks. 52faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI * The MDC clock selection macros need to be defined for MDC clock rate 53faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI * of 12.5 MHz, corresponding to the following selection. 5418f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO */ 5518f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ 5618f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ 5718f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ 5818f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ 5918f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ 6018f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ 6118f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ 6218f05d64ec36e27892cc0f55be707762aae053a1Giuseppe CAVALLARO#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ 63faeae3fa0f3a243f677cf606aa87d0d99c225165Deepak SIKRI 6402582e9bcc36ed503ffede46e104a885dea222fbMasanari Iida/* AXI DMA Burst length supported */ 658327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI#define DMA_AXI_BLEN_4 (1 << 1) 668327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI#define DMA_AXI_BLEN_8 (1 << 2) 678327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI#define DMA_AXI_BLEN_16 (1 << 3) 688327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI#define DMA_AXI_BLEN_32 (1 << 4) 698327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI#define DMA_AXI_BLEN_64 (1 << 5) 708327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI#define DMA_AXI_BLEN_128 (1 << 6) 718327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI#define DMA_AXI_BLEN_256 (1 << 7) 728327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ 738327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ 748327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) 758327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI 7636bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO/* Platfrom data for platform device structure's platform_data field */ 7736bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO 7836bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLAROstruct stmmac_mdio_bus_data { 7936bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO int (*phy_reset)(void *priv); 8036bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO unsigned int phy_mask; 8136bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO int *irqs; 8236bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO int probed_phy_irq; 830e0764715d8116484d808f5b3985ca043080788eSrinivas Kandagatla#ifdef CONFIG_OF 840e0764715d8116484d808f5b3985ca043080788eSrinivas Kandagatla int reset_gpio, active_low; 850e0764715d8116484d808f5b3985ca043080788eSrinivas Kandagatla u32 delays[3]; 860e0764715d8116484d808f5b3985ca043080788eSrinivas Kandagatla#endif 8736bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO}; 883c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO 898327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRIstruct stmmac_dma_cfg { 908327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI int pbl; 918327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI int fixed_burst; 92b9cde0a8be876c680cc549daa6246256864473fbGiuseppe CAVALLARO int mixed_burst; 938327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI int burst_len; 948327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI}; 958327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI 963c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLAROstruct plat_stmmacenet_data { 97f142af2e2064546ac470e8690acbd189b3584e67Srinivas Kandagatla char *phy_bus_name; 983c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO int bus_id; 9936bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO int phy_addr; 10036bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO int interface; 10136bcfe7d74782c07f601edc4831f6b1ef40e9e43Giuseppe CAVALLARO struct stmmac_mdio_bus_data *mdio_bus_data; 1028327eb65e795ba4f922bf7e531cd312875f0dc29Deepak SIKRI struct stmmac_dma_cfg *dma_cfg; 103dfb8fb96ae2b5126cd0c08c0ccd7c42e1f46568aGiuseppe CAVALLARO int clk_csr; 1043c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO int has_gmac; 105e326e8503dfc73e4f79d488a78ee3d7cde10081fGiuseppe CAVALLARO int enh_desc; 106ebbb293f8b3021ae2009fcb7cb3b8a52fb5fd06aGiuseppe CAVALLARO int tx_coe; 10755f9a4d6facb35198ddb88a8fe21ca2ee753af7aDeepak SIKRI int rx_coe; 108ebbb293f8b3021ae2009fcb7cb3b8a52fb5fd06aGiuseppe CAVALLARO int bugged_jumbo; 109543876c92837a8b208b5c99ec225c1f5a581900eGiuseppe Cavallaro int pmt; 11061b8013a114cb041db2c56f747953cac69637f26Srinivas Kandagatla int force_sf_dma_mode; 111e2a240c7d3bcebf90936cc7c22c2729b3a4cec1fSonic Zhang int force_thresh_dma_mode; 11262a2ab935c8d0f8643d02d3696abc401b5da6206Giuseppe CAVALLARO int riwt_off; 1139cbadf094d9d479413dc8cfa77dff9e732184337Srinivas Kandagatla int max_speed; 1142618abb73c8953f0848511fc13f68da4d8337574Vince Bridgers int maxmtu; 1153b57de958e2aa39abe020eb31bf19000d5899389Vince Bridgers int multicast_filter_bins; 1163b57de958e2aa39abe020eb31bf19000d5899389Vince Bridgers int unicast_filter_entries; 1173c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO void (*fix_mac_speed)(void *priv, unsigned int speed); 118ad01b7d480a4a135f974afd5c617c417e0b0542fGiuseppe CAVALLARO void (*bus_setup)(void __iomem *ioaddr); 119938dfdaa3c0f92e9a490d324f3bce43bbaef7632Chen-Yu Tsai void *(*setup)(struct platform_device *pdev); 120938dfdaa3c0f92e9a490d324f3bce43bbaef7632Chen-Yu Tsai void (*free)(struct platform_device *pdev, void *priv); 121938dfdaa3c0f92e9a490d324f3bce43bbaef7632Chen-Yu Tsai int (*init)(struct platform_device *pdev, void *priv); 122938dfdaa3c0f92e9a490d324f3bce43bbaef7632Chen-Yu Tsai void (*exit)(struct platform_device *pdev, void *priv); 123293bb1c41b728d4aa248fe8a0acd2b9066ff5c34Giuseppe CAVALLARO void *custom_cfg; 1243256251f9850d00c8e4a4fd82440092bb0f1fd7dFrancesco Virlinzi void *custom_data; 1253c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO void *bsp_priv; 1263c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO}; 127022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai 128022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai/* of_data for SoC glue layer device tree bindings */ 129022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai 130022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsaistruct stmmac_of_data { 131022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai int has_gmac; 132022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai int enh_desc; 133022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai int tx_coe; 134022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai int rx_coe; 135022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai int bugged_jumbo; 136022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai int pmt; 137022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai int riwt_off; 138022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai void (*fix_mac_speed)(void *priv, unsigned int speed); 139022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai void (*bus_setup)(void __iomem *ioaddr); 140022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai void *(*setup)(struct platform_device *pdev); 141022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai void (*free)(struct platform_device *pdev, void *priv); 142022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai int (*init)(struct platform_device *pdev, void *priv); 143022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai void (*exit)(struct platform_device *pdev, void *priv); 144022066f50f53000679d31eb407693085f37b3f14Chen-Yu Tsai}; 1453c9732c06879d85f2fdf7ec69198c1d78da42a98Giuseppe CAVALLARO#endif 146