params.h revision eb5ef07151ba3c3cb4bcef0c8f146ff1115eaa55 
1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a copy
3 * of this software and associated documentation files (the "Software"), to
4 * deal in the Software without restriction, including without limitation the
5 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
6 * sell copies of the Software, and to permit persons to whom the Software is
7 * furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
15 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
16 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
17 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
18 * DEALINGS IN THE SOFTWARE.
19 */
20
21#ifndef __XEN_PUBLIC_HVM_PARAMS_H__
22#define __XEN_PUBLIC_HVM_PARAMS_H__
23
24#include "hvm_op.h"
25
26/*
27 * Parameter space for HVMOP_{set,get}_param.
28 */
29
30/*
31 * How should CPU0 event-channel notifications be delivered?
32 * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).
33 * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:
34 *                  Domain = val[47:32], Bus  = val[31:16],
35 *                  DevFn  = val[15: 8], IntX = val[ 1: 0]
36 * val[63:56] == 2: val[7:0] is a vector number.
37 * If val == 0 then CPU0 event-channel notifications are not delivered.
38 */
39#define HVM_PARAM_CALLBACK_IRQ 0
40
41#define HVM_PARAM_STORE_PFN    1
42#define HVM_PARAM_STORE_EVTCHN 2
43
44#define HVM_PARAM_PAE_ENABLED  4
45
46#define HVM_PARAM_IOREQ_PFN    5
47
48#define HVM_PARAM_BUFIOREQ_PFN 6
49
50/*
51 * Set mode for virtual timers (currently x86 only):
52 *  delay_for_missed_ticks (default):
53 *   Do not advance a vcpu's time beyond the correct delivery time for
54 *   interrupts that have been missed due to preemption. Deliver missed
55 *   interrupts when the vcpu is rescheduled and advance the vcpu's virtual
56 *   time stepwise for each one.
57 *  no_delay_for_missed_ticks:
58 *   As above, missed interrupts are delivered, but guest time always tracks
59 *   wallclock (i.e., real) time while doing so.
60 *  no_missed_ticks_pending:
61 *   No missed interrupts are held pending. Instead, to ensure ticks are
62 *   delivered at some non-zero rate, if we detect missed ticks then the
63 *   internal tick alarm is not disabled if the VCPU is preempted during the
64 *   next tick period.
65 *  one_missed_tick_pending:
66 *   Missed interrupts are collapsed together and delivered as one 'late tick'.
67 *   Guest time always tracks wallclock (i.e., real) time.
68 */
69#define HVM_PARAM_TIMER_MODE   10
70#define HVMPTM_delay_for_missed_ticks    0
71#define HVMPTM_no_delay_for_missed_ticks 1
72#define HVMPTM_no_missed_ticks_pending   2
73#define HVMPTM_one_missed_tick_pending   3
74
75/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
76#define HVM_PARAM_HPET_ENABLED 11
77
78/* Identity-map page directory used by Intel EPT when CR0.PG=0. */
79#define HVM_PARAM_IDENT_PT     12
80
81/* Device Model domain, defaults to 0. */
82#define HVM_PARAM_DM_DOMAIN    13
83
84/* ACPI S state: currently support S0 and S3 on x86. */
85#define HVM_PARAM_ACPI_S_STATE 14
86
87/* TSS used on Intel when CR0.PE=0. */
88#define HVM_PARAM_VM86_TSS     15
89
90/* Boolean: Enable aligning all periodic vpts to reduce interrupts */
91#define HVM_PARAM_VPT_ALIGN    16
92
93/* Console debug shared memory ring and event channel */
94#define HVM_PARAM_CONSOLE_PFN    17
95#define HVM_PARAM_CONSOLE_EVTCHN 18
96
97#define HVM_NR_PARAMS          19
98
99#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
100