Cross Reference: /drivers/gpu/drm/i915/i915_gem

Lines Matching defs:args
287 	struct drm_i915_gem_set_tiling *args = data;
292 	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
297 			    args->stride, obj->base.size, args->tiling_mode)) {
307 	if (args->tiling_mode == I915_TILING_NONE) {
308 		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
309 		args->stride = 0;
311 		if (args->tiling_mode == I915_TILING_X)
312 			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
314 			args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
323 		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
324 			args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
325 		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
326 			args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
329 		if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
330 			args->tiling_mode = I915_TILING_NONE;
331 			args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
332 			args->stride = 0;
337 	if (args->tiling_mode != obj->tiling_mode ||
338 	    args->stride != obj->stride) {
349 			 i915_gem_object_fence_ok(obj, args->tiling_mode));
356 								    args->tiling_mode);
363 			obj->tiling_mode = args->tiling_mode;
364 			obj->stride = args->stride;
368 	args->stride = obj->stride;
369 	args->tiling_mode = obj->tiling_mode;
383 	struct drm_i915_gem_get_tiling *args = data;
387 	obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
393 	args->tiling_mode = obj->tiling_mode;
396 		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
399 		args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
402 		args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
409 	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
410 		args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
411 	if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
412 		args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;