Lines Matching refs:CRTC
46 crtcstate->CRTC[index]);
55 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
57 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
58 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
334 * CRTC
336 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
337 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
338 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
339 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
341 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
342 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
344 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
345 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
353 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
354 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
357 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
358 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
359 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
360 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
361 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
362 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
363 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
364 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
365 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
367 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
368 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
369 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
370 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
371 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
372 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
375 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
379 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
381 regp->CRTC[NV_CIO_CRE_42] =
383 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
385 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
390 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
394 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
401 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
402 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
404 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
446 * The clocks, CRTCs and outputs attached to this CRTC must be off.
484 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
509 regp->CRTC[NV_CIO_CRE_53] = 0;
510 regp->CRTC[NV_CIO_CRE_54] = 0;
514 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
516 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
518 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
522 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
532 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
536 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
538 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
542 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
545 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
564 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
565 regp->CRTC[NV_CIO_CRE_86] = 0x1;
568 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8;
571 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
602 * The clocks, CRTCs and outputs attached to this CRTC must be off.
616 NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index);
647 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
657 uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
829 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
830 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8;
838 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
839 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
841 regp->CRTC[NV_CIO_CRE_42] =
856 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
857 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
862 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;