Lines Matching defs:pll
79 read_pll(struct drm_device *dev, int clk, u32 pll)
81 u32 ctrl = nv_rd32(dev, pll + 0);
86 u32 coef = nv_rd32(dev, pll + 4);
92 if ((pll & 0x00ff00) == 0x00e800)
106 u32 pll;
110 calc_clk(struct drm_device *dev, int clk, u32 pll, u32 khz, struct creg *reg)
117 reg->pll = 0;
120 NV_DEBUG(dev, "no clock for 0x%04x/0x%02x\n", pll, clk);
148 if (!pll || (diff >= -2000 && diff < 3000)) {
154 if (!pll) {
162 ret = get_pll_limits(dev, pll, &limits);
173 reg->pll = (P << 16) | (N << 8) | M;
179 prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg)
183 const u32 ctrl = pll + 0;
184 const u32 coef = pll + 4;
187 if (!reg->clk && !reg->pll) {
193 if (reg->pll) {
195 nv_wr32(dev, coef, reg->pll);
319 if (info->mclk.clk || info->mclk.pll) {