Lines Matching refs:regs

42 	u8 regs[8];
100 static int stv6110_read_regs(struct dvb_frontend *fe, u8 regs[],
115 .buf = regs,
130 memcpy(&priv->regs[start], regs, len);
185 priv->regs[RSTV6110_CTRL3] &= ~((1 << 6) | 0x1f);
186 priv->regs[RSTV6110_CTRL3] |= (r8 & 0x1f);
187 stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL3], RSTV6110_CTRL3, 1);
189 priv->regs[RSTV6110_STAT1] |= 0x02;
190 stv6110_write_regs(fe, &priv->regs[RSTV6110_STAT1], RSTV6110_STAT1, 1);
201 priv->regs[RSTV6110_CTRL3] |= (1 << 6);
202 stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL3], RSTV6110_CTRL3, 1);
211 memcpy(priv->regs, buf0, 8);
213 priv->regs[RSTV6110_CTRL1] &= ~(0x1f << 3);
214 priv->regs[RSTV6110_CTRL1] |=
218 priv->regs[RSTV6110_CTRL2] &= ~0xc0;
219 priv->regs[RSTV6110_CTRL2] |= (priv->clk_div << 6);
221 stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL1], RSTV6110_CTRL1, 8);
232 u8 regs[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
234 stv6110_read_regs(fe, regs, 0, 8);
236 divider = (priv->regs[RSTV6110_TUNING2] & 0x0f) << 8;
237 divider += priv->regs[RSTV6110_TUNING1];
240 nbsteps = (priv->regs[RSTV6110_TUNING2] >> 6) & 3;
242 psd2 = (priv->regs[RSTV6110_TUNING2] >> 4) & 1;
266 priv->regs[RSTV6110_CTRL1] &= ~(0x1f << 3);
267 priv->regs[RSTV6110_CTRL1] |=
278 priv->regs[RSTV6110_CTRL2] &= ~0x0f;
279 priv->regs[RSTV6110_CTRL2] |= (priv->gain & 0x0f);
295 priv->regs[RSTV6110_TUNING2] &= ~(1 << 4);
296 priv->regs[RSTV6110_TUNING2] |= (p << 4);
299 priv->regs[RSTV6110_TUNING2] &= ~(1 << 5);
300 priv->regs[RSTV6110_TUNING2] |= (presc << 5);
317 priv->regs[RSTV6110_TUNING2] &= ~(3 << 6);
318 priv->regs[RSTV6110_TUNING2] |= (((r_div_opt) & 3) << 6);
321 priv->regs[RSTV6110_TUNING2] &= ~0x0f;
322 priv->regs[RSTV6110_TUNING2] |= (((divider) >> 8) & 0x0f);
325 priv->regs[RSTV6110_TUNING1] = (divider & 0xff);
328 priv->regs[RSTV6110_STAT1] |= 0x04;
329 stv6110_write_regs(fe, &priv->regs[RSTV6110_CTRL1],
365 u8 regs[] = { 0, 0, 0, 0, 0, 0, 0, 0 };
366 stv6110_read_regs(fe, regs, 0, 8);
369 r8 = priv->regs[RSTV6110_CTRL3] & 0x1f;
435 memcpy(&priv->regs, &reg0[1], 8);