Lines Matching defs:rb
51 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,
53 static enum bfa_status bfa_ioc_ct2_pll_init(void __iomem *rb,
257 void __iomem *rb;
260 rb = bfa_ioc_bar0(ioc);
262 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox;
263 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox;
264 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn;
267 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
268 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
269 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
270 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn;
271 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu;
272 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
273 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
275 ioc->ioc_regs.heartbeat = rb + BFA_IOC1_HBEAT_REG;
276 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC1_STATE_REG;
277 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
278 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn;
279 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu;
280 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
281 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
287 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG;
288 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG;
289 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + APP_PLL_LCLK_CTL_REG;
290 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + APP_PLL_SCLK_CTL_REG;
295 ioc->ioc_regs.ioc_sem_reg = rb + HOST_SEM0_REG;
296 ioc->ioc_regs.ioc_usage_sem_reg = rb + HOST_SEM1_REG;
297 ioc->ioc_regs.ioc_init_sem_reg = rb + HOST_SEM2_REG;
298 ioc->ioc_regs.ioc_usage_reg = rb + BFA_FW_USE_COUNT;
299 ioc->ioc_regs.ioc_fail_sync = rb + BFA_IOC_FAIL_SYNC;
304 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START;
310 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
316 void __iomem *rb;
319 rb = bfa_ioc_bar0(ioc);
321 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox;
322 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox;
323 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn;
324 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn;
325 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu;
326 ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read;
329 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG;
330 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;
331 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG;
332 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
333 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
335 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC1_HBEAT_REG;
336 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG;
337 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;
338 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
339 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
345 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG;
346 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG;
347 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + CT2_APP_PLL_LCLK_CTL_REG;
348 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + CT2_APP_PLL_SCLK_CTL_REG;
353 ioc->ioc_regs.ioc_sem_reg = rb + CT2_HOST_SEM0_REG;
354 ioc->ioc_regs.ioc_usage_sem_reg = rb + CT2_HOST_SEM1_REG;
355 ioc->ioc_regs.ioc_init_sem_reg = rb + CT2_HOST_SEM2_REG;
356 ioc->ioc_regs.ioc_usage_reg = rb + CT2_BFA_FW_USE_COUNT;
357 ioc->ioc_regs.ioc_fail_sync = rb + CT2_BFA_IOC_FAIL_SYNC;
362 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START;
368 ioc->ioc_regs.err_set = rb + ERR_SET_REG;
379 void __iomem *rb = ioc->pcidev.pci_bar_kva;
385 r32 = readl(rb + FNC_PERS_REG);
394 void __iomem *rb = ioc->pcidev.pci_bar_kva;
397 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0);
407 void __iomem *rb = ioc->pcidev.pci_bar_kva;
410 r32 = readl(rb + FNC_PERS_REG);
429 writel(r32, rb + FNC_PERS_REG);
459 void __iomem *rb = ioc->pcidev.pci_bar_kva;
462 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT);
465 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);
471 rb + HOSTFN_MSIX_VT_OFST_NUMVT);
473 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);
593 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
608 writel(0, (rb + OP_MODE));
612 (rb + ETH_MAC_SER_REG));
614 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
616 (rb + ETH_MAC_SER_REG));
618 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
619 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
620 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
621 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
622 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
623 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
624 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
625 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
628 rb + APP_PLL_SCLK_CTL_REG);
631 rb + APP_PLL_LCLK_CTL_REG);
634 rb + APP_PLL_SCLK_CTL_REG);
637 rb + APP_PLL_LCLK_CTL_REG);
638 readl(rb + HOSTFN0_INT_MSK);
640 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
641 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
644 rb + APP_PLL_SCLK_CTL_REG);
647 rb + APP_PLL_LCLK_CTL_REG);
650 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
651 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
653 r32 = readl((rb + PSS_CTL_REG));
655 writel(r32, (rb + PSS_CTL_REG));
658 writel(0, (rb + PMM_1T_RESET_REG_P0));
659 writel(0, (rb + PMM_1T_RESET_REG_P1));
662 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
664 r32 = readl((rb + MBIST_STAT_REG));
665 writel(0, (rb + MBIST_CTL_REG));
670 bfa_ioc_ct2_sclk_init(void __iomem *rb)
677 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
681 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
687 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
689 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
694 r32 = readl((rb + CT2_CHIP_MISC_PRG));
696 (rb + CT2_CHIP_MISC_PRG));
698 r32 = readl((rb + CT2_PCIE_MISC_REG));
700 (rb + CT2_PCIE_MISC_REG));
705 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
708 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));
722 bfa_ioc_ct2_lclk_init(void __iomem *rb)
729 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
733 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
738 r32 = readl((rb + CT2_CHIP_MISC_PRG));
739 writel(r32, (rb + CT2_CHIP_MISC_PRG));
744 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
745 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
750 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
753 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
762 bfa_ioc_ct2_mem_init(void __iomem *rb)
766 r32 = readl((rb + PSS_CTL_REG));
768 writel(r32, (rb + PSS_CTL_REG));
771 writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));
773 writel(0, (rb + CT2_MBIST_CTL_REG));
777 bfa_ioc_ct2_mac_reset(void __iomem *rb)
781 bfa_ioc_ct2_sclk_init(rb);
782 bfa_ioc_ct2_lclk_init(rb);
787 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
789 (rb + CT2_APP_PLL_SCLK_CTL_REG));
794 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
796 (rb + CT2_APP_PLL_LCLK_CTL_REG));
800 (rb + CT2_CSI_MAC_CONTROL_REG(0)));
802 (rb + CT2_CSI_MAC_CONTROL_REG(1)));
807 bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode)
815 wgn = readl(rb + CT2_WGN_STATUS);
817 writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG));
819 r32 = readl(rb + CT2_NFC_CSR_SET_REG);
831 writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));
832 writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));
834 r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
836 writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));
837 readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
839 r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
841 writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));
842 readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
845 bfa_ioc_ct2_mac_reset(rb);
846 bfa_ioc_ct2_sclk_init(rb);
847 bfa_ioc_ct2_lclk_init(rb);
852 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
854 (rb + CT2_APP_PLL_SCLK_CTL_REG));
859 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
861 (rb + CT2_APP_PLL_LCLK_CTL_REG));
867 r32 = readl((rb + PSS_GPIO_OUT_REG));
868 writel((r32 & ~1), (rb + PSS_GPIO_OUT_REG));
869 r32 = readl((rb + PSS_GPIO_OE_REG));
870 writel((r32 | 1), (rb + PSS_GPIO_OE_REG));
873 bfa_ioc_ct2_mem_init(rb);
875 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));
876 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));