Cross Reference: /drivers/net/ethernet/ibm/emac/phy.c

Lines Matching defs:phy
2  * drivers/net/ibm_newemac/phy.c
29 #include "phy.h"
34 static inline int _phy_read(struct mii_phy *phy, int reg)
36 	return phy->mdio_read(phy->dev, phy->address, reg);
39 static inline void _phy_write(struct mii_phy *phy, int reg, int val)
41 	phy->mdio_write(phy->dev, phy->address, reg, val);
44 static inline int gpcs_phy_read(struct mii_phy *phy, int reg)
46 	return phy->mdio_read(phy->dev, phy->gpcs_address, reg);
49 static inline void gpcs_phy_write(struct mii_phy *phy, int reg, int val)
51 	phy->mdio_write(phy->dev, phy->gpcs_address, reg, val);
54 int emac_mii_reset_phy(struct mii_phy *phy)
59 	val = phy_read(phy, MII_BMCR);
62 	phy_write(phy, MII_BMCR, val);
67 		val = phy_read(phy, MII_BMCR);
73 		phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
78 int emac_mii_reset_gpcs(struct mii_phy *phy)
83 	val = gpcs_phy_read(phy, MII_BMCR);
86 	gpcs_phy_write(phy, MII_BMCR, val);
91 		val = gpcs_phy_read(phy, MII_BMCR);
97 		gpcs_phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
99 	if (limit > 0 && phy->mode == PHY_MODE_SGMII) {
101 		gpcs_phy_write(phy, 0x04, 0x8120); /* AsymPause, FDX */
102 		gpcs_phy_write(phy, 0x07, 0x2801); /* msg_pg, toggle */
103 		gpcs_phy_write(phy, 0x00, 0x0140); /* 1Gbps, FDX     */
109 static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
113 	phy->autoneg = AUTONEG_ENABLE;
114 	phy->speed = SPEED_10;
115 	phy->duplex = DUPLEX_HALF;
116 	phy->pause = phy->asym_pause = 0;
117 	phy->advertising = advertise;
119 	ctl = phy_read(phy, MII_BMCR);
125 	phy_write(phy, MII_BMCR, ctl);
128 	adv = phy_read(phy, MII_ADVERTISE);
145 	phy_write(phy, MII_ADVERTISE, adv);
147 	if (phy->features &
149 		adv = phy_read(phy, MII_CTRL1000);
157 		phy_write(phy, MII_CTRL1000, adv);
161 	ctl = phy_read(phy, MII_BMCR);
163 	phy_write(phy, MII_BMCR, ctl);
168 static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
172 	phy->autoneg = AUTONEG_DISABLE;
173 	phy->speed = speed;
174 	phy->duplex = fd;
175 	phy->pause = phy->asym_pause = 0;
177 	ctl = phy_read(phy, MII_BMCR);
183 	phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
200 	phy_write(phy, MII_BMCR, ctl);
205 static int genmii_poll_link(struct mii_phy *phy)
210 	phy_read(phy, MII_BMSR);
211 	status = phy_read(phy, MII_BMSR);
214 	if (phy->autoneg == AUTONEG_ENABLE && !(status & BMSR_ANEGCOMPLETE))
219 static int genmii_read_link(struct mii_phy *phy)
221 	if (phy->autoneg == AUTONEG_ENABLE) {
223 		int lpa = phy_read(phy, MII_LPA) & phy_read(phy, MII_ADVERTISE);
227 		if (phy->features &
229 			int adv = phy_read(phy, MII_CTRL1000);
230 			glpa = phy_read(phy, MII_STAT1000);
238 		phy->speed = SPEED_10;
239 		phy->duplex = DUPLEX_HALF;
240 		phy->pause = phy->asym_pause = 0;
243 			phy->speed = SPEED_1000;
245 				phy->duplex = DUPLEX_FULL;
247 			phy->speed = SPEED_100;
249 				phy->duplex = DUPLEX_FULL;
251 			phy->duplex = DUPLEX_FULL;
253 		if (phy->duplex == DUPLEX_FULL) {
254 			phy->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
255 			phy->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
258 		int bmcr = phy_read(phy, MII_BMCR);
263 			phy->duplex = DUPLEX_FULL;
265 			phy->duplex = DUPLEX_HALF;
267 			phy->speed = SPEED_1000;
269 			phy->speed = SPEED_100;
271 			phy->speed = SPEED_10;
273 		phy->pause = phy->asym_pause = 0;
305 static int cis8201_init(struct mii_phy *phy)
309 	epcr = phy_read(phy, MII_CIS8201_EPCR);
315 	switch (phy->mode) {
330 	phy_write(phy, MII_CIS8201_EPCR, epcr);
333 	phy_write(phy, MII_CIS8201_ACSR,
334 		  phy_read(phy, MII_CIS8201_ACSR) | ACSR_PIN_PRIO_SELECT);
337 	phy_write(phy, MII_CIS8201_10BTCSR,
338 		  phy_read(phy, MII_CIS8201_10BTCSR) | TENBTCSR_ECHO_DISABLE);
366 static int m88e1111_init(struct mii_phy *phy)
369 	phy_write(phy, 0x14, 0x0ce3);
370 	phy_write(phy, 0x18, 0x4101);
371 	phy_write(phy, 0x09, 0x0e00);
372 	phy_write(phy, 0x04, 0x01e1);
373 	phy_write(phy, 0x00, 0x9140);
374 	phy_write(phy, 0x00, 0x1140);
379 static int m88e1112_init(struct mii_phy *phy)
392 	phy_write(phy, 0x16, 0x0002);
394 	phy_write(phy, 0x00, 0x0040); /* 1Gbps */
395 	reg_short = (u16)(phy_read(phy, 0x1a));
397 	phy_write(phy, 0x1a, reg_short);
398 	emac_mii_reset_phy(phy); /* reset MAC interface */
401 	phy_write(phy, 0x16, 0x0000);
406 static int et1011c_init(struct mii_phy *phy)
410 	reg_short = (u16)(phy_read(phy, 0x16));
413 	phy_write(phy, 0x16, reg_short);
415 	reg_short = (u16)(phy_read(phy, 0x17));
417 	phy_write(phy, 0x17, reg_short);
419 	phy_write(phy, 0x1c, 0x74f0);
483 int emac_mii_phy_probe(struct mii_phy *phy, int address)
489 	phy->autoneg = AUTONEG_DISABLE;
490 	phy->advertising = 0;
491 	phy->address = address;
492 	phy->speed = SPEED_10;
493 	phy->duplex = DUPLEX_HALF;
494 	phy->pause = phy->asym_pause = 0;
497 	if (emac_mii_reset_phy(phy))
501 	id = (phy_read(phy, MII_PHYSID1) << 16) | phy_read(phy, MII_PHYSID2);
509 	phy->def = def;
512 	phy->features = def->features;
513 	if (!phy->features) {
514 		u16 bmsr = phy_read(phy, MII_BMSR);
516 			phy->features |= SUPPORTED_Autoneg;
518 			phy->features |= SUPPORTED_10baseT_Half;
520 			phy->features |= SUPPORTED_10baseT_Full;
522 			phy->features |= SUPPORTED_100baseT_Half;
524 			phy->features |= SUPPORTED_100baseT_Full;
526 			u16 esr = phy_read(phy, MII_ESTATUS);
528 				phy->features |= SUPPORTED_1000baseT_Full;
530 				phy->features |= SUPPORTED_1000baseT_Half;
532 		phy->features |= SUPPORTED_MII;
536 	phy->advertising = phy->features;