Lines Matching defs:efx
21 #include "efx.h"
56 struct efx_nic *efx = (struct efx_nic *)data;
59 efx_reado(efx, ®, FR_AB_GPIO_CTL);
61 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
66 struct efx_nic *efx = (struct efx_nic *)data;
69 efx_reado(efx, ®, FR_AB_GPIO_CTL);
71 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
76 struct efx_nic *efx = (struct efx_nic *)data;
79 efx_reado(efx, ®, FR_AB_GPIO_CTL);
85 struct efx_nic *efx = (struct efx_nic *)data;
88 efx_reado(efx, ®, FR_AB_GPIO_CTL);
105 struct efx_nic *efx = channel->efx;
123 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
127 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
129 static void falcon_prepare_flush(struct efx_nic *efx)
131 falcon_deconfigure_mac_wrapper(efx);
149 inline void falcon_irq_ack_a1(struct efx_nic *efx)
154 efx_writed(efx, ®, FR_AA_INT_ACK_KER);
155 efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
161 struct efx_nic *efx = dev_id;
162 efx_oword_t *int_ker = efx->irq_status.addr;
170 netif_vdbg(efx, intr, efx->net_dev,
175 efx->last_irq_cpu = raw_smp_processor_id();
176 netif_vdbg(efx, intr, efx->net_dev,
187 if (queues & (1U << efx->fatal_irq_level)) {
190 return efx_nic_fatal_interrupt(efx);
195 falcon_irq_ack_a1(efx);
198 efx_schedule_channel(efx_get_channel(efx, 0));
200 efx_schedule_channel(efx_get_channel(efx, 1));
212 static int falcon_spi_poll(struct efx_nic *efx)
215 efx_reado(efx, ®, FR_AB_EE_SPI_HCMD);
220 static int falcon_spi_wait(struct efx_nic *efx)
230 if (!falcon_spi_poll(efx))
236 if (!falcon_spi_poll(efx))
239 netif_err(efx, hw, efx->net_dev,
247 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
261 rc = falcon_spi_poll(efx);
268 efx_writeo(efx, ®, FR_AB_EE_SPI_HADR);
274 efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA);
287 efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD);
290 rc = falcon_spi_wait(efx);
296 efx_reado(efx, ®, FR_AB_EE_SPI_HDATA);
319 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
326 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
333 netif_err(efx, hw, efx->net_dev,
343 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
354 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
374 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
383 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
390 rc = falcon_spi_cmd(efx, spi, command, start + pos,
395 rc = falcon_spi_wait_write(efx, spi);
400 rc = falcon_spi_cmd(efx, spi, command, start + pos,
429 static void falcon_push_multicast_hash(struct efx_nic *efx)
431 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
433 WARN_ON(!mutex_is_locked(&efx->mac_lock));
435 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
436 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
439 static void falcon_reset_macs(struct efx_nic *efx)
441 struct falcon_nic_data *nic_data = efx->nic_data;
445 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
450 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
453 efx_reado(efx, ®, FR_AB_XM_GLB_CFG);
460 netif_err(efx, hw, efx->net_dev,
467 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
469 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
471 efx_reado(efx, ®, FR_AB_GLB_CTL);
475 efx_writeo(efx, ®, FR_AB_GLB_CTL);
479 efx_reado(efx, ®, FR_AB_GLB_CTL);
483 netif_dbg(efx, hw, efx->net_dev,
489 netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
498 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
500 falcon_setup_xaui(efx);
503 void falcon_drain_tx_fifo(struct efx_nic *efx)
507 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
508 (efx->loopback_mode != LOOPBACK_NONE))
511 efx_reado(efx, ®, FR_AB_MAC_CTRL);
516 falcon_reset_macs(efx);
519 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
523 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
527 efx_reado(efx, ®, FR_AZ_RX_CFG);
529 efx_writeo(efx, ®, FR_AZ_RX_CFG);
532 falcon_drain_tx_fifo(efx);
535 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
537 struct efx_link_state *link_state = &efx->link_state;
541 isolate = !!ACCESS_ONCE(efx->reset_pending);
556 FRF_AB_MAC_UC_PROM, efx->promiscuous,
561 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
566 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
569 falcon_push_multicast_hash(efx);
571 efx_reado(efx, ®, FR_AZ_RX_CFG);
576 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
578 efx_writeo(efx, ®, FR_AZ_RX_CFG);
581 static void falcon_stats_request(struct efx_nic *efx)
583 struct falcon_nic_data *nic_data = efx->nic_data;
600 efx->stats_buffer.dma_addr);
601 efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA);
606 static void falcon_stats_complete(struct efx_nic *efx)
608 struct falcon_nic_data *nic_data = efx->nic_data;
616 efx->mac_op->update_stats(efx);
618 netif_err(efx, hw, efx->net_dev,
625 struct efx_nic *efx = (struct efx_nic *)context;
626 struct falcon_nic_data *nic_data = efx->nic_data;
628 spin_lock(&efx->stats_lock);
630 falcon_stats_complete(efx);
632 falcon_stats_request(efx);
634 spin_unlock(&efx->stats_lock);
637 static bool falcon_loopback_link_poll(struct efx_nic *efx)
639 struct efx_link_state old_state = efx->link_state;
641 WARN_ON(!mutex_is_locked(&efx->mac_lock));
642 WARN_ON(!LOOPBACK_INTERNAL(efx));
644 efx->link_state.fd = true;
645 efx->link_state.fc = efx->wanted_fc;
646 efx->link_state.up = true;
647 efx->link_state.speed = 10000;
649 return !efx_link_state_equal(&efx->link_state, &old_state);
652 static int falcon_reconfigure_port(struct efx_nic *efx)
656 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
662 if (LOOPBACK_INTERNAL(efx))
663 falcon_loopback_link_poll(efx);
665 efx->phy_op->poll(efx);
667 falcon_stop_nic_stats(efx);
668 falcon_deconfigure_mac_wrapper(efx);
670 falcon_reset_macs(efx);
672 efx->phy_op->reconfigure(efx);
673 rc = efx->mac_op->reconfigure(efx);
676 falcon_start_nic_stats(efx);
678 /* Synchronise efx->link_state with the kernel */
679 efx_link_status_changed(efx);
692 static int falcon_gmii_wait(struct efx_nic *efx)
699 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
703 netif_err(efx, hw, efx->net_dev,
713 netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
721 struct efx_nic *efx = netdev_priv(net_dev);
722 struct falcon_nic_data *nic_data = efx->nic_data;
726 netif_vdbg(efx, hw, efx->net_dev,
733 rc = falcon_gmii_wait(efx);
739 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
743 efx_writeo(efx, ®, FR_AB_MD_ID);
747 efx_writeo(efx, ®, FR_AB_MD_TXD);
752 efx_writeo(efx, ®, FR_AB_MD_CS);
755 rc = falcon_gmii_wait(efx);
761 efx_writeo(efx, ®, FR_AB_MD_CS);
774 struct efx_nic *efx = netdev_priv(net_dev);
775 struct falcon_nic_data *nic_data = efx->nic_data;
782 rc = falcon_gmii_wait(efx);
787 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
791 efx_writeo(efx, ®, FR_AB_MD_ID);
795 efx_writeo(efx, ®, FR_AB_MD_CS);
798 rc = falcon_gmii_wait(efx);
800 efx_reado(efx, ®, FR_AB_MD_RXD);
802 netif_vdbg(efx, hw, efx->net_dev,
810 efx_writeo(efx, ®, FR_AB_MD_CS);
812 netif_dbg(efx, hw, efx->net_dev,
823 static int falcon_probe_port(struct efx_nic *efx)
825 struct falcon_nic_data *nic_data = efx->nic_data;
828 switch (efx->phy_type) {
830 efx->phy_op = &falcon_sfx7101_phy_ops;
834 efx->phy_op = &falcon_qt202x_phy_ops;
837 efx->phy_op = &falcon_txc_phy_ops;
840 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
841 efx->phy_type);
847 efx->mdio.mdio_read = falcon_mdio_read;
848 efx->mdio.mdio_write = falcon_mdio_write;
849 rc = efx->phy_op->probe(efx);
854 efx->link_state.speed = 10000;
855 efx->link_state.fd = true;
858 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
859 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
861 efx->wanted_fc = EFX_FC_RX;
862 if (efx->mdio.mmds & MDIO_DEVS_AN)
863 efx->wanted_fc |= EFX_FC_AUTO;
866 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
870 netif_dbg(efx, probe, efx->net_dev,
872 (u64)efx->stats_buffer.dma_addr,
873 efx->stats_buffer.addr,
874 (u64)virt_to_phys(efx->stats_buffer.addr));
875 nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset;
880 static void falcon_remove_port(struct efx_nic *efx)
882 efx->phy_op->remove(efx);
883 efx_nic_free_buffer(efx, &efx->stats_buffer);
890 struct efx_nic *efx = channel->efx;
891 struct falcon_nic_data *nic_data = efx->nic_data;
899 if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
905 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
908 netif_err(efx, rx_err, efx->net_dev,
912 atomic_inc(&efx->rx_reset);
913 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
928 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
930 struct falcon_nic_data *nic_data = efx->nic_data;
951 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
954 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
966 netif_err(efx, hw, efx->net_dev,
971 netif_err(efx, hw, efx->net_dev,
985 netif_err(efx, hw, efx->net_dev,
999 static int falcon_test_nvram(struct efx_nic *efx)
1001 return falcon_read_nvram(efx, NULL);
1043 static int falcon_b0_test_registers(struct efx_nic *efx)
1045 return efx_nic_test_registers(efx, falcon_b0_register_tests,
1101 static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1103 struct falcon_nic_data *nic_data = efx->nic_data;
1107 netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1112 rc = pci_save_state(efx->pci_dev);
1114 netif_err(efx, drv, efx->net_dev,
1119 if (efx_nic_is_dual_func(efx)) {
1122 netif_err(efx, drv, efx->net_dev,
1148 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1150 netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1155 if (efx_nic_is_dual_func(efx))
1157 pci_restore_state(efx->pci_dev);
1158 netif_dbg(efx, drv, efx->net_dev,
1163 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1166 netif_err(efx, hw, efx->net_dev,
1170 netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
1176 pci_restore_state(efx->pci_dev);
1182 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1184 struct falcon_nic_data *nic_data = efx->nic_data;
1188 rc = __falcon_reset_hw(efx, method);
1194 static void falcon_monitor(struct efx_nic *efx)
1199 BUG_ON(!mutex_is_locked(&efx->mac_lock));
1201 rc = falcon_board(efx)->type->monitor(efx);
1203 netif_err(efx, hw, efx->net_dev,
1206 efx->phy_mode |= PHY_MODE_LOW_POWER;
1207 rc = __efx_reconfigure_port(efx);
1211 if (LOOPBACK_INTERNAL(efx))
1212 link_changed = falcon_loopback_link_poll(efx);
1214 link_changed = efx->phy_op->poll(efx);
1217 falcon_stop_nic_stats(efx);
1218 falcon_deconfigure_mac_wrapper(efx);
1220 falcon_reset_macs(efx);
1221 rc = efx->mac_op->reconfigure(efx);
1224 falcon_start_nic_stats(efx);
1226 efx_link_status_changed(efx);
1229 falcon_poll_xmac(efx);
1235 static int falcon_reset_sram(struct efx_nic *efx)
1241 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1244 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1250 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1255 netif_dbg(efx, hw, efx->net_dev,
1262 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1264 netif_dbg(efx, hw, efx->net_dev,
1271 netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
1275 static void falcon_spi_device_init(struct efx_nic *efx,
1301 static int falcon_probe_nvconfig(struct efx_nic *efx)
1303 struct falcon_nic_data *nic_data = efx->nic_data;
1311 rc = falcon_read_nvram(efx, nvconfig);
1315 efx->phy_type = nvconfig->board_v2.port0_phy_type;
1316 efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
1320 efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1324 efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1330 memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN);
1332 netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
1333 efx->phy_type, efx->mdio.prtad);
1335 rc = falcon_probe_board(efx,
1343 static void falcon_probe_spi_devices(struct efx_nic *efx)
1345 struct falcon_nic_data *nic_data = efx->nic_data;
1349 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1350 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1351 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1356 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
1363 netif_dbg(efx, probe, efx->net_dev,
1371 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1377 falcon_spi_device_init(efx, &nic_data->spi_flash,
1381 falcon_spi_device_init(efx, &nic_data->spi_eeprom,
1386 static int falcon_probe_nic(struct efx_nic *efx)
1396 efx->nic_data = nic_data;
1400 if (efx_nic_fpga_ver(efx) != 0) {
1401 netif_err(efx, probe, efx->net_dev,
1406 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1409 u8 pci_rev = efx->pci_dev->revision;
1412 netif_err(efx, probe, efx->net_dev,
1416 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1418 netif_err(efx, probe, efx->net_dev,
1423 netif_err(efx, probe, efx->net_dev,
1428 dev = pci_dev_get(efx->pci_dev);
1432 if (dev->bus == efx->pci_dev->bus &&
1433 dev->devfn == efx->pci_dev->devfn + 1) {
1439 netif_err(efx, probe, efx->net_dev,
1447 rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
1449 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
1454 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1457 BUG_ON(efx->irq_status.dma_addr & 0x0f);
1459 netif_dbg(efx, probe, efx->net_dev,
1461 (u64)efx->irq_status.dma_addr,
1462 efx->irq_status.addr,
1463 (u64)virt_to_phys(efx->irq_status.addr));
1465 falcon_probe_spi_devices(efx);
1468 rc = falcon_probe_nvconfig(efx);
1471 netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
1476 board = falcon_board(efx);
1479 board->i2c_data.data = efx;
1481 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1488 rc = falcon_board(efx)->type->init(efx);
1490 netif_err(efx, probe, efx->net_dev,
1497 (unsigned long)efx);
1505 efx_nic_free_buffer(efx, &efx->irq_status);
1514 kfree(efx->nic_data);
1518 static void falcon_init_rx_cfg(struct efx_nic *efx)
1529 efx_reado(efx, ®, FR_AZ_RX_CFG);
1530 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1561 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1568 static int falcon_init_nic(struct efx_nic *efx)
1574 efx_reado(efx, &temp, FR_AB_NIC_STAT);
1576 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1578 rc = falcon_reset_sram(efx);
1585 if (EFX_WORKAROUND_5129(efx)) {
1586 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1588 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1591 if (EFX_WORKAROUND_7244(efx)) {
1592 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1597 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1604 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1607 if (EFX_WORKAROUND_5583(efx))
1609 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1614 efx_reado(efx, &temp, FR_AZ_TX_CFG);
1616 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1618 falcon_init_rx_cfg(efx);
1620 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1622 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
1623 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
1627 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1630 efx_nic_init_common(efx);
1635 static void falcon_remove_nic(struct efx_nic *efx)
1637 struct falcon_nic_data *nic_data = efx->nic_data;
1638 struct falcon_board *board = falcon_board(efx);
1641 board->type->fini(efx);
1648 efx_nic_free_buffer(efx, &efx->irq_status);
1650 __falcon_reset_hw(efx, RESET_TYPE_ALL);
1659 kfree(efx->nic_data);
1660 efx->nic_data = NULL;
1663 static void falcon_update_nic_stats(struct efx_nic *efx)
1665 struct falcon_nic_data *nic_data = efx->nic_data;
1671 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1672 efx->n_rx_nodesc_drop_cnt +=
1679 efx->mac_op->update_stats(efx);
1683 void falcon_start_nic_stats(struct efx_nic *efx)
1685 struct falcon_nic_data *nic_data = efx->nic_data;
1687 spin_lock_bh(&efx->stats_lock);
1689 falcon_stats_request(efx);
1690 spin_unlock_bh(&efx->stats_lock);
1693 void falcon_stop_nic_stats(struct efx_nic *efx)
1695 struct falcon_nic_data *nic_data = efx->nic_data;
1700 spin_lock_bh(&efx->stats_lock);
1702 spin_unlock_bh(&efx->stats_lock);
1714 spin_lock_bh(&efx->stats_lock);
1715 falcon_stats_complete(efx);
1716 spin_unlock_bh(&efx->stats_lock);
1719 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1721 falcon_board(efx)->type->set_id_led(efx, mode);
1731 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1738 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1747 * Revision-dependent attributes used by efx.c and nic.c