Lines Matching defs:REGISTERS_BASE
30 #define REGISTERS_BASE 0x00300000
60 #define ACX_REG_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
62 #define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
63 #define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
64 #define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
66 #define ACX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
67 #define ACX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
97 #define ACX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
107 #define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
117 #define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
128 #define ACX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
139 #define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
151 #define ACX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
153 #define RX_DRIVER_COUNTER_ADDRESS (REGISTERS_BASE + 0x0538)
156 #define SOR_CFG (REGISTERS_BASE + 0x0800)
178 #define ACX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
180 #define HI_CFG (REGISTERS_BASE + 0x0808)
197 #define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
199 #define OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
200 #define OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
201 #define OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
202 #define OCP_CMD (REGISTERS_BASE + 0x09C0)
204 #define WL1271_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
206 #define CHIP_ID_B (REGISTERS_BASE + 0x5674)
213 #define ENABLE (REGISTERS_BASE + 0x5450)
216 #define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
217 #define ELP_CMD (REGISTERS_BASE + 0x5808)
218 #define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
219 #define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
220 #define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
222 #define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
225 #define SCR_PAD0 (REGISTERS_BASE + 0x5608)
226 #define SCR_PAD1 (REGISTERS_BASE + 0x560C)
227 #define SCR_PAD2 (REGISTERS_BASE + 0x5610)
228 #define SCR_PAD3 (REGISTERS_BASE + 0x5614)
229 #define SCR_PAD4 (REGISTERS_BASE + 0x5618)
230 #define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
231 #define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
232 #define SCR_PAD5 (REGISTERS_BASE + 0x5624)
233 #define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
234 #define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
235 #define SCR_PAD6 (REGISTERS_BASE + 0x5630)
236 #define SCR_PAD7 (REGISTERS_BASE + 0x5634)
237 #define SCR_PAD8 (REGISTERS_BASE + 0x5638)
238 #define SCR_PAD9 (REGISTERS_BASE + 0x563C)
241 #define SPARE_A1 (REGISTERS_BASE + 0x0994)
242 #define SPARE_A2 (REGISTERS_BASE + 0x0998)
243 #define SPARE_A3 (REGISTERS_BASE + 0x099C)
244 #define SPARE_A4 (REGISTERS_BASE + 0x09A0)
245 #define SPARE_A5 (REGISTERS_BASE + 0x09A4)
246 #define SPARE_A6 (REGISTERS_BASE + 0x09A8)
247 #define SPARE_A7 (REGISTERS_BASE + 0x09AC)
248 #define SPARE_A8 (REGISTERS_BASE + 0x09B0)
249 #define SPARE_B1 (REGISTERS_BASE + 0x5420)
250 #define SPARE_B2 (REGISTERS_BASE + 0x5424)
251 #define SPARE_B3 (REGISTERS_BASE + 0x5428)
252 #define SPARE_B4 (REGISTERS_BASE + 0x542C)
253 #define SPARE_B5 (REGISTERS_BASE + 0x5430)
254 #define SPARE_B6 (REGISTERS_BASE + 0x5434)
255 #define SPARE_B7 (REGISTERS_BASE + 0x5438)
256 #define SPARE_B8 (REGISTERS_BASE + 0x543C)
258 #define PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
259 #define WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
260 #define WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)