Lines Matching refs:regs

51 	u8			regs[15];
72 fm3130->regs[FM3130_RTC_CONTROL] =
76 fm3130->regs[FM3130_RTC_CONTROL] &=
81 fm3130->regs[FM3130_RTC_CONTROL] |= FM3130_RTC_CONTROL_BIT_WRITE;
84 fm3130->regs[FM3130_RTC_CONTROL] |= FM3130_RTC_CONTROL_BIT_READ;
92 FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL]);
122 fm3130->regs[0], fm3130->regs[1],
123 fm3130->regs[2], fm3130->regs[3],
124 fm3130->regs[4], fm3130->regs[5],
125 fm3130->regs[6], fm3130->regs[7],
126 fm3130->regs[8], fm3130->regs[9],
127 fm3130->regs[0xa], fm3130->regs[0xb],
128 fm3130->regs[0xc], fm3130->regs[0xd],
129 fm3130->regs[0xe]);
131 t->tm_sec = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
132 t->tm_min = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
133 tmp = fm3130->regs[FM3130_RTC_HOURS] & 0x3f;
135 t->tm_wday = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x07) - 1;
136 t->tm_mday = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
137 tmp = fm3130->regs[FM3130_RTC_MONTHS] & 0x1f;
141 t->tm_year = bcd2bin(fm3130->regs[FM3130_RTC_YEARS]) + 100;
158 u8 *buf = fm3130->regs;
191 fm3130->regs[FM3130_RTC_SECONDS + i]);
226 fm3130->regs[FM3130_ALARM_SECONDS],
227 fm3130->regs[FM3130_ALARM_MINUTES],
228 fm3130->regs[FM3130_ALARM_HOURS],
229 fm3130->regs[FM3130_ALARM_DATE],
230 fm3130->regs[FM3130_ALARM_MONTHS]);
232 tm->tm_sec = bcd2bin(fm3130->regs[FM3130_ALARM_SECONDS] & 0x7F);
233 tm->tm_min = bcd2bin(fm3130->regs[FM3130_ALARM_MINUTES] & 0x7F);
234 tm->tm_hour = bcd2bin(fm3130->regs[FM3130_ALARM_HOURS] & 0x3F);
235 tm->tm_mday = bcd2bin(fm3130->regs[FM3130_ALARM_DATE] & 0x3F);
236 tm->tm_mon = bcd2bin(fm3130->regs[FM3130_ALARM_MONTHS] & 0x1F);
248 fm3130->regs[FM3130_RTC_CONTROL] =
251 if ((fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_AEN) &&
252 (~fm3130->regs[FM3130_RTC_CONTROL] &
272 fm3130->regs[FM3130_ALARM_SECONDS] =
275 fm3130->regs[FM3130_ALARM_MINUTES] =
278 fm3130->regs[FM3130_ALARM_HOURS] =
281 fm3130->regs[FM3130_ALARM_DATE] =
284 fm3130->regs[FM3130_ALARM_MONTHS] =
288 fm3130->regs[FM3130_ALARM_SECONDS],
289 fm3130->regs[FM3130_ALARM_MINUTES],
290 fm3130->regs[FM3130_ALARM_HOURS],
291 fm3130->regs[FM3130_ALARM_DATE],
292 fm3130->regs[FM3130_ALARM_MONTHS]);
297 fm3130->regs[FM3130_ALARM_SECONDS + i]);
299 fm3130->regs[FM3130_RTC_CONTROL] =
305 (fm3130->regs[FM3130_RTC_CONTROL] &
310 fm3130->regs[FM3130_RTC_CONTROL] &
327 fm3130->regs[FM3130_RTC_CONTROL] =
331 enabled, fm3130->regs[FM3130_RTC_CONTROL]);
336 FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL] &
342 FM3130_RTC_CONTROL, (fm3130->regs[FM3130_RTC_CONTROL] &
395 fm3130->msg[1].buf = &fm3130->regs[FM3130_RTC_SECONDS];
406 fm3130->msg[3].buf = &fm3130->regs[FM3130_ALARM_SECONDS];
418 fm3130->regs[FM3130_RTC_CONTROL] =
420 fm3130->regs[FM3130_CAL_CONTROL] =
424 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_CAL) {
426 fm3130->regs[FM3130_RTC_CONTROL] &
432 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_WRITE ||
433 fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_READ) {
435 fm3130->regs[FM3130_RTC_CONTROL] &
442 if (fm3130->regs[FM3130_CAL_CONTROL] & FM3130_CAL_CONTROL_BIT_nOSCEN)
444 fm3130->regs[FM3130_CAL_CONTROL] &
448 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_LB) {
450 fm3130->regs[FM3130_RTC_CONTROL] &
456 if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_POR) {
458 fm3130->regs[FM3130_RTC_CONTROL] &
466 tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
470 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
474 tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
478 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
482 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
491 tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
495 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
499 tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
503 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x7);
507 tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
511 tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
524 fm3130->regs[0], fm3130->regs[1],
525 fm3130->regs[2], fm3130->regs[3],
526 fm3130->regs[4], fm3130->regs[5],
527 fm3130->regs[6], fm3130->regs[7],
528 fm3130->regs[8], fm3130->regs[9],
529 fm3130->regs[0xa], fm3130->regs[0xb],
530 fm3130->regs[0xc], fm3130->regs[0xd],
531 fm3130->regs[0xe]);