Lines Matching defs:rb
200 void __iomem *rb;
203 rb = bfa_ioc_bar0(ioc);
205 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox;
206 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox;
207 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn;
210 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
211 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
212 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
213 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn;
214 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu;
215 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
216 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
218 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
219 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
220 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
221 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn;
222 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu;
223 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
224 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
230 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
231 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
232 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
233 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
238 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
239 ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
240 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
241 ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
242 ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
247 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
253 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
259 void __iomem *rb;
262 rb = bfa_ioc_bar0(ioc);
264 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox;
265 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox;
266 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn;
267 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn;
268 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu;
269 ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read;
272 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG;
273 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;
274 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG;
275 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
276 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
278 ioc->ioc_regs.heartbeat = (rb + CT2_BFA_IOC1_HBEAT_REG);
279 ioc->ioc_regs.ioc_fwstate = (rb + CT2_BFA_IOC1_STATE_REG);
280 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG;
281 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
282 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
288 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
289 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
290 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + CT2_APP_PLL_LCLK_CTL_REG);
291 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + CT2_APP_PLL_SCLK_CTL_REG);
296 ioc->ioc_regs.ioc_sem_reg = (rb + CT2_HOST_SEM0_REG);
297 ioc->ioc_regs.ioc_usage_sem_reg = (rb + CT2_HOST_SEM1_REG);
298 ioc->ioc_regs.ioc_init_sem_reg = (rb + CT2_HOST_SEM2_REG);
299 ioc->ioc_regs.ioc_usage_reg = (rb + CT2_BFA_FW_USE_COUNT);
300 ioc->ioc_regs.ioc_fail_sync = (rb + CT2_BFA_IOC_FAIL_SYNC);
305 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
311 ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
322 void __iomem *rb = ioc->pcidev.pci_bar_kva;
328 r32 = readl(rb + FNC_PERS_REG);
339 void __iomem *rb = ioc->pcidev.pci_bar_kva;
342 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0);
355 void __iomem *rb = ioc->pcidev.pci_bar_kva;
358 r32 = readl(rb + FNC_PERS_REG);
379 writel(r32, rb + FNC_PERS_REG);
576 void __iomem *rb = ioc->pcidev.pci_bar_kva;
579 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT);
582 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);
588 rb + HOSTFN_MSIX_VT_OFST_NUMVT);
590 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR);
594 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
609 writel(0, (rb + OP_MODE));
611 __APP_EMS_CHANNEL_SEL, (rb + ETH_MAC_SER_REG));
613 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE));
614 writel(__APP_EMS_REFCKBUFEN1, (rb + ETH_MAC_SER_REG));
616 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG));
617 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG));
618 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
619 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
620 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
621 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
622 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
623 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
625 rb + APP_PLL_SCLK_CTL_REG);
627 rb + APP_PLL_LCLK_CTL_REG);
629 __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG);
631 __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG);
632 readl(rb + HOSTFN0_INT_MSK);
634 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
635 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
636 writel(pll_sclk | __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG);
637 writel(pll_fclk | __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG);
640 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0));
641 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1));
643 r32 = readl((rb + PSS_CTL_REG));
645 writel(r32, (rb + PSS_CTL_REG));
648 writel(0, (rb + PMM_1T_RESET_REG_P0));
649 writel(0, (rb + PMM_1T_RESET_REG_P1));
652 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG));
654 r32 = readl((rb + MBIST_STAT_REG));
655 writel(0, (rb + MBIST_CTL_REG));
660 bfa_ioc_ct2_sclk_init(void __iomem *rb)
667 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
671 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
677 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
679 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG));
684 r32 = readl((rb + CT2_CHIP_MISC_PRG));
685 writel(r32 | __ETH_CLK_ENABLE_PORT0, (rb + CT2_CHIP_MISC_PRG));
687 r32 = readl((rb + CT2_PCIE_MISC_REG));
688 writel(r32 | __ETH_CLK_ENABLE_PORT1, (rb + CT2_PCIE_MISC_REG));
693 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
696 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG));
705 bfa_ioc_ct2_lclk_init(void __iomem *rb)
712 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
716 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
721 r32 = readl((rb + CT2_CHIP_MISC_PRG));
722 writel(r32, (rb + CT2_CHIP_MISC_PRG));
727 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
728 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
733 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
736 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG));
745 bfa_ioc_ct2_mem_init(void __iomem *rb)
749 r32 = readl((rb + PSS_CTL_REG));
751 writel(r32, (rb + PSS_CTL_REG));
754 writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG));
756 writel(0, (rb + CT2_MBIST_CTL_REG));
760 bfa_ioc_ct2_mac_reset(void __iomem *rb)
764 bfa_ioc_ct2_sclk_init(rb);
765 bfa_ioc_ct2_lclk_init(rb);
770 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
772 (rb + CT2_APP_PLL_SCLK_CTL_REG));
777 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
779 (rb + CT2_APP_PLL_LCLK_CTL_REG));
783 rb + CT2_CSI_MAC_CONTROL_REG(0));
785 rb + CT2_CSI_MAC_CONTROL_REG(1));
790 bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode)
798 wgn = readl(rb + CT2_WGN_STATUS);
800 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG);
802 r32 = readl(rb + CT2_NFC_CSR_SET_REG);
813 writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK));
814 writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK));
816 r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
818 writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT));
819 readl((rb + CT2_LPU0_HOSTFN_CMD_STAT));
821 r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
823 writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT));
824 readl((rb + CT2_LPU1_HOSTFN_CMD_STAT));
827 bfa_ioc_ct2_mac_reset(rb);
828 bfa_ioc_ct2_sclk_init(rb);
829 bfa_ioc_ct2_lclk_init(rb);
834 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG));
836 (rb + CT2_APP_PLL_SCLK_CTL_REG));
841 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG));
843 (rb + CT2_APP_PLL_LCLK_CTL_REG));
849 r32 = readl((rb + PSS_GPIO_OUT_REG));
850 writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG));
851 r32 = readl((rb + PSS_GPIO_OE_REG));
852 writel(r32 | 1, (rb + PSS_GPIO_OE_REG));
855 bfa_ioc_ct2_mem_init(rb);
857 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG));
858 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG));