Searched defs:reg_base (Results 1 - 25 of 36) sorted by relevance

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/drivers/staging/tidspbridge/include/dspbridge/
H A Dwdt.h27 * @reg_base: pointer to the base of the wdt registers
37 void __iomem *reg_base; member in struct:dsp_wdt_setting
/drivers/usb/host/
H A Dohci-octeon.c109 void *reg_base; local
147 reg_base = ioremap(hcd->rsrc_start, hcd->rsrc_len);
148 if (!reg_base) {
156 hcd->regs = reg_base;
H A Dehci-pmcmsp.c49 struct ehci_regs *reg_base = ehci->regs; local
52 base = (u8 *)reg_base + USB_EHCI_REG_USB_MODE;
53 statreg = (u8 *)reg_base + USB_EHCI_REG_USB_STATUS;
54 fiforeg = (u8 *)reg_base + USB_EHCI_REG_USB_FIFO;
/drivers/i2c/busses/
H A Di2c-sibyte.c33 void *reg_base; /* CSR base */ member in struct:i2c_algo_sibyte_data
37 #define SMB_CSR(a,r) ((long)(a->reg_base + r))
H A Di2c-pca-platform.c31 void __iomem *reg_base; member in struct:i2c_pca_pf_data
46 return ioread8(i2c->reg_base + reg);
52 return ioread8(i2c->reg_base + reg * 2);
58 return ioread8(i2c->reg_base + reg * 4);
64 iowrite8(val, i2c->reg_base + reg);
70 iowrite8(val, i2c->reg_base + reg * 2);
76 iowrite8(val, i2c->reg_base + reg * 4);
165 i2c->reg_base = ioremap(res->start, resource_size(res));
166 if (!i2c->reg_base) {
250 iounmap(i2c->reg_base);
[all...]
H A Di2c-mv64xxx.c89 void __iomem *reg_base; member in struct:mv64xxx_i2c_data
119 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
121 drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
122 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
123 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
125 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
245 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
252 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
257 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
262 drv_data->reg_base
[all...]
H A Di2c-pxa.c150 void __iomem *reg_base; member in struct:pxa_i2c
1092 i2c->reg_base = ioremap(res->start, resource_size(res));
1093 if (!i2c->reg_base) {
1098 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1099 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1100 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1101 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1103 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1168 iounmap(i2c->reg_base);
1191 iounmap(i2c->reg_base);
[all...]
/drivers/ide/
H A Dopti621.c29 static int reg_base; variable
34 * is at reg_base (0x1f0 primary, 0x170 secondary,
40 inw(reg_base + 1);
41 inw(reg_base + 1);
42 outb(3, reg_base + 2);
43 outb(value, reg_base + reg);
44 outb(0x83, reg_base + 2);
48 * is at reg_base (0x1f0 primary, 0x170 secondary,
56 inw(reg_base + 1);
57 inw(reg_base
[all...]
/drivers/net/can/sja1000/
H A Dpeak_pci.c76 return readb(priv->reg_base + (port << 2));
82 writeb(val, priv->reg_base + (port << 2));
102 void __iomem *cfg_base, *reg_base; local
140 reg_base = pci_iomap(pdev, 1, PEAK_PCI_CHAN_SIZE * channels);
141 if (!reg_base) {
169 priv->reg_base = reg_base + i * PEAK_PCI_CHAN_SIZE;
203 "%s at reg_base=0x%p cfg_base=0x%p irq=%d\n",
204 dev->name, priv->reg_base, chan->cfg_base, dev->irq);
223 pci_iounmap(pdev, reg_base);
243 void __iomem *reg_base = priv->reg_base; local
[all...]
H A Dsja1000.h167 void __iomem *reg_base; /* ioremap'ed address to registers */ member in struct:sja1000_priv
/drivers/input/keyboard/
H A Dnomadik-ske-keypad.c55 * @reg_base: ske regsiters base address
63 void __iomem *reg_base; member in struct:ske_keypad
78 ret = readl(keypad->reg_base + addr);
81 writel(ret, keypad->reg_base + addr);
97 while ((readl(keypad->reg_base + SKE_RIS) != 0x00000000) && timeout--)
109 value = readl(keypad->reg_base + SKE_DBCR);
112 writel(value, keypad->reg_base + SKE_DBCR);
152 ske_asr = readl(keypad->reg_base + SKE_ASR0 + (4 * i));
169 ske_ris = readl(keypad->reg_base + SKE_RIS);
187 while ((readl(keypad->reg_base
[all...]
/drivers/spi/
H A Dspi-fsl-lib.h26 void *reg_base; member in struct:mpc8xxx_spi
H A Dspi-fsl-espi.c91 struct fsl_espi_reg *reg_base = mspi->reg_base; local
92 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
93 __be32 __iomem *espi_mode = &reg_base->mode;
206 struct fsl_espi_reg *reg_base = mspi->reg_base; local
211 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
215 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
223 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base; local
458 struct fsl_espi_reg *reg_base; local
508 struct fsl_espi_reg *reg_base = mspi->reg_base; local
568 struct fsl_espi_reg *reg_base = mspi->reg_base; local
595 struct fsl_espi_reg *reg_base; local
[all...]
/drivers/gpio/
H A Dgpio-langwell.c49 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
67 void *reg_base; member in struct:lnw_gpio
81 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
93 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
347 lnw->reg_base = base;
419 lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
420 if (lnw->reg_base == NULL) {
445 iounmap(lnw->reg_base);
458 iounmap(lnw->reg_base);
/drivers/mfd/
H A Dtwl4030-madc.c211 * @reg_base - Base address of the first channel
218 u8 reg_base, unsigned
225 reg = reg_base + 2 * i;
217 twl4030_madc_read_channels(struct twl4030_madc_data *madc, u8 reg_base, unsigned long channels, int *buf) argument
/drivers/usb/musb/
H A Dda8xx.c147 void __iomem *reg_base = musb->ctrl_base; local
154 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
158 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
167 void __iomem *reg_base = musb->ctrl_base; local
169 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
173 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
296 void __iomem *reg_base = musb->ctrl_base; local
309 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
313 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
329 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_RE
416 void __iomem *reg_base = musb->ctrl_base; local
[all...]
H A Dam35x.c98 void __iomem *reg_base = musb->ctrl_base; local
105 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
106 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
119 void __iomem *reg_base = musb->ctrl_base; local
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
225 void __iomem *reg_base = musb->ctrl_base; local
236 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_RE
355 void __iomem *reg_base = musb->ctrl_base; local
[all...]
/drivers/dma/ioat/
H A Ddma.h43 #define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
54 * @reg_base: MMIO register space base address
72 void __iomem *reg_base; member in struct:ioatdma_device
90 void __iomem *reg_base; member in struct:ioat_chan_common
235 status_lo = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_LOW(ver));
236 status = readl(chan->reg_base + IOAT_CHANSTS_OFFSET_HIGH(ver));
247 writeb(IOAT_CHANCMD_START, chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
257 return readl(chan->reg_base + IOAT_CHANERR_OFFSET);
264 writeb(IOAT_CHANCMD_SUSPEND, chan->reg_base
[all...]
H A Ddma.c65 intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET);
71 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
75 attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET);
81 writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET);
107 chan->reg_base = device->reg_base + (0x80 * (idx + 1));
133 dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET);
140 xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET);
172 void __iomem *reg_base = ioat->base.reg_base; local
198 void __iomem *reg_base = chan->reg_base; local
[all...]
/drivers/pcmcia/
H A Dm32r_cfc.c319 unsigned int reg_base; local
321 reg_base = (unsigned int)PLD_CFRSTCR;
322 reg_base |= pcc_sockets << 8;
323 request_region(reg_base, 0x20, "m32r_cfc");
/drivers/input/misc/
H A Dad714x.c917 unsigned short reg_base; local
923 reg_base = AD714X_STAGECFG_REG + i * STAGE_CFGREG_NUM;
925 ad714x->write(ad714x, reg_base + j,
/drivers/net/can/cc770/
H A Dcc770.h188 void __iomem *reg_base; /* ioremap'ed address to registers */ member in struct:cc770_priv
/drivers/net/can/mscan/
H A Dmscan.h286 void __iomem *reg_base; /* ioremap'ed address to registers */ member in struct:mscan_priv
/drivers/rtc/
H A Drtc-x1205.c93 unsigned char reg_base)
95 unsigned char dt_addr[2] = { 0, reg_base };
118 if (reg_base < X1205_CCR_BASE)
159 u8 reg_base, unsigned char alm_enable)
162 unsigned char rdata[10] = { 0, reg_base };
195 if (reg_base < X1205_CCR_BASE)
220 if (reg_base < X1205_CCR_BASE) {
92 x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm, unsigned char reg_base) argument
158 x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm, u8 reg_base, unsigned char alm_enable) argument
/drivers/scsi/bnx2fc/
H A Dbnx2fc_hwi.c1426 resource_size_t reg_base; local
1430 reg_base = pci_resource_start(hba->pcidev,
1434 tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4);

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