Searched defs:spll (Results 1 - 5 of 5) sorted by relevance

/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c37 struct radeon_pll *spll = &rdev->clock.spll; local
43 fb_div *= spll->reference_freq;
106 struct radeon_pll *spll = &rdev->clock.spll; local
145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq;
146 spll->reference_div = mpll->reference_div =
181 struct radeon_pll *spll = &rdev->clock.spll; local
209 if (spll
350 struct radeon_pll *spll = &rdev->clock.spll; local
[all...]
H A Dradeon_atombios.c1107 struct radeon_pll *spll = &rdev->clock.spll; local
1160 spll->reference_freq =
1163 spll->reference_freq =
1165 spll->reference_div = 0;
1167 spll->pll_out_min =
1169 spll->pll_out_max =
1173 if (spll->pll_out_min == 0) {
1175 spll->pll_out_min = 64800;
1177 spll
[all...]
H A Dradeon_combios.c803 struct radeon_pll *spll = &rdev->clock.spll; local
830 spll->reference_freq = RBIOS16(pll_info + 0x1a);
831 spll->reference_div = RBIOS16(pll_info + 0x1c);
832 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
833 spll->pll_out_max = RBIOS32(pll_info + 0x22);
836 spll->pll_in_min = RBIOS32(pll_info + 0x48);
837 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
840 spll->pll_in_min = 40;
841 spll
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H A Dradeon.h218 struct radeon_pll spll; member in struct:radeon_clock
/drivers/gpu/drm/nouveau/
H A Dnv40_pm.c103 u32 spll; member in struct:nv40_pm_state
174 info->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1;
177 info->spll = 0x00000000;
272 nv_mask(dev, 0x004008, 0xc007ffff, info->spll);

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