Searched refs:CCR0 (Results 1 - 2 of 2) sorted by relevance

/drivers/net/wan/
H A Ddscc4.c270 #define CCR0 0x08 macro
614 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
629 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
860 scc_writel(0x00000000, dpriv, dev, CCR0);
1078 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1088 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1141 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1198 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1226 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1246 * Clock mode related bits of CCR0
[all...]
/drivers/char/pcmcia/
H A Dsynclink_cs.c270 #define CCR0 0x2c macro
2938 /* CCR0
2948 write_reg(info, CHB + CCR0, 0xc0);
3081 /* CCR0
3107 write_reg(info, CHA + CCR0, val);
3257 clear_reg_bits(info, CHA + CCR0, BIT6);
3349 write_reg(info, CHA + CCR0, 0x80);
3350 write_reg(info, CHB + CCR0, 0x80);
3427 /* CCR0
3437 write_reg(info, CHA + CCR0,
[all...]

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