Searched refs:CNTR (Results 1 - 8 of 8) sorted by relevance

/drivers/scsi/
H A Dgvp11.h30 volatile unsigned short CNTR; member in struct:gvp11_scsiregs
46 /* bits in CNTR */
H A Da2091.h31 volatile unsigned short CNTR; member in struct:a2091_scsiregs
51 /* CNTR bits. */
H A Da3000.h33 volatile unsigned short CNTR; member in struct:a3000_scsiregs
53 /* CNTR bits. */
H A Dgvp11.c31 unsigned int status = hdata->regs->CNTR;
122 regs->CNTR = cntr;
156 regs->CNTR = GVP11_DMAC_INT_ENABLE;
332 while (regs->CNTR & GVP11_DMAC_BUSY)
334 regs->CNTR = 0;
364 regs->CNTR = GVP11_DMAC_INT_ENABLE;
388 hdata->regs->CNTR = 0;
H A Da2091.c88 regs->CNTR = cntr;
121 regs->CNTR = cntr;
137 regs->CNTR = CNTR_PDMD | CNTR_INTEN;
222 regs->CNTR = CNTR_PDMD | CNTR_INTEN;
247 hdata->regs->CNTR = 0;
H A Da3000.c87 regs->CNTR = cntr;
122 regs->CNTR = cntr;
123 mb(); /* make sure CNTR is updated before next IO */
145 regs->CNTR = CNTR_PDMD | CNTR_INTEN;
146 mb(); /* make sure CNTR is updated before next IO */
240 regs->CNTR = CNTR_PDMD | CNTR_INTEN;
266 hdata->regs->CNTR = 0;
/drivers/dma/
H A Dtxx9dmac.h77 TXX9_DMA_REG32(CNTR); /* Count Register */
87 u32 CNTR; member in struct:txx9dmac_cregs32
212 TXX9_DMA_REG32(CNTR);
218 u32 CNTR; member in struct:txx9dmac_hwdesc32
H A Dtxx9dmac.c303 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
308 channel64_readl(dc, CNTR),
315 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
320 channel32_readl(dc, CNTR),
339 channel_writel(dc, CNTR, 0);
365 channel64_writel(dc, CNTR, 0);
386 channel32_writel(dc, CNTR, 0);
518 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
523 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
531 d->CHAR, d->SAR, d->DAR, d->CNTR);
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