/drivers/gpu/drm/nouveau/ |
H A D | nvc0_fbcon.c | 47 OUT_RING (chan, 1); 52 OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); 54 OUT_RING (chan, rect->color); 56 OUT_RING (chan, rect->dx); 57 OUT_RING (chan, rect->dy); 58 OUT_RING (chan, rect->dx + rect->width); 59 OUT_RING (chan, rect->dy + rect->height); 62 OUT_RING (chan, 3); 82 OUT_RING (chan, 0); 84 OUT_RING (cha [all...] |
H A D | nv50_fbcon.c | 47 OUT_RING(chan, 1); 52 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); 54 OUT_RING(chan, rect->color); 56 OUT_RING(chan, rect->dx); 57 OUT_RING(chan, rect->dy); 58 OUT_RING(chan, rect->dx + rect->width); 59 OUT_RING(chan, rect->dy + rect->height); 62 OUT_RING(chan, 3); 82 OUT_RING(chan, 0); 84 OUT_RING(cha [all...] |
H A D | nv04_fbcon.c | 45 OUT_RING(chan, (region->sy << 16) | region->sx); 46 OUT_RING(chan, (region->dy << 16) | region->dx); 47 OUT_RING(chan, (region->height << 16) | region->width); 66 OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); 70 OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); 72 OUT_RING(chan, rect->color); 74 OUT_RING(chan, (rect->dx << 16) | rect->dy); 75 OUT_RING(chan, (rect->width << 16) | rect->height); 114 OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); 115 OUT_RING(cha [all...] |
H A D | nv50_cursor.c | 57 OUT_RING(evo, NvEvoVRAM); 60 OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_SHOW); 61 OUT_RING(evo, nv_crtc->cursor.offset >> 8); 65 OUT_RING(evo, 0); 90 OUT_RING(evo, NV50_EVO_CRTC_CURSOR_CTRL_HIDE); 91 OUT_RING(evo, 0); 94 OUT_RING(evo, NV84_EVO_CRTC_CURSOR_DMA_HANDLE_NONE); 99 OUT_RING(evo, 0);
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H A D | nv50_display.c | 121 OUT_RING (evo, 0x80000000); 123 OUT_RING (evo, 0); 125 OUT_RING (evo, 0x00000000); 248 OUT_RING (evo, NV50_EVO_UNK84_NOTIFY_DISABLED); 249 OUT_RING (evo, NvEvoSync); 273 OUT_RING(evo, 0); 419 OUT_RING (evo, 0x00000000); 421 OUT_RING (evo, 0x00000000); 423 OUT_RING (evo, 0x00000000); 425 OUT_RING (ev [all...] |
H A D | nouveau_fence.c | 174 OUT_RING (chan, fence->sequence); 348 OUT_RING (chan, NvSema); 349 OUT_RING (chan, offset); 350 OUT_RING (chan, 1); 358 OUT_RING (chan, chan->vram_handle); 360 OUT_RING (chan, upper_32_bits(offset)); 361 OUT_RING (chan, lower_32_bits(offset)); 362 OUT_RING (chan, 1); 363 OUT_RING (chan, 1); /* ACQUIRE_EQ */ 370 OUT_RING (cha [all...] |
H A D | nv50_crtc.c | 83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK); 84 OUT_RING(evo, 0); 87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE); 91 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE); 104 OUT_RING(evo, nv_crtc->lut.depth == 8 ? 107 OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8); 110 OUT_RING(evo, NvEvoVRAM); 114 OUT_RING(evo, nv_crtc->fb.offset >> 8); 115 OUT_RING(evo, 0); 120 OUT_RING(ev [all...] |
H A D | nouveau_bo.c | 505 OUT_RING (chan, upper_32_bits(dst_offset)); 506 OUT_RING (chan, lower_32_bits(dst_offset)); 508 OUT_RING (chan, upper_32_bits(src_offset)); 509 OUT_RING (chan, lower_32_bits(src_offset)); 510 OUT_RING (chan, PAGE_SIZE); /* src_pitch */ 511 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ 512 OUT_RING (chan, PAGE_SIZE); /* line_length */ 513 OUT_RING (chan, line_count); 515 OUT_RING (chan, 0x00100110); 550 OUT_RING (cha [all...] |
H A D | nouveau_dma.h | 116 OUT_RING(struct nouveau_channel *chan, int data) function 132 OUT_RING(chan, (op << 28) | (size << 16) | (subc << 13) | (mthd >> 2)); 138 OUT_RING(chan, (subc << 13) | (size << 18) | mthd);
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H A D | nouveau_dma.c | 74 OUT_RING (chan, 0x00009039); 97 OUT_RING(chan, 0); 104 OUT_RING (chan, NvM2MF); 106 OUT_RING (chan, NvNotify0); 107 OUT_RING (chan, chan->vram_handle); 108 OUT_RING (chan, chan->gart_handle); 311 OUT_RING(chan, chan->pushbuf_base | 0x20000000);
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H A D | nv50_dac.c | 59 OUT_RING (evo, 0); 61 OUT_RING (evo, 0); 247 OUT_RING(evo, mode_ctl); 248 OUT_RING(evo, mode_ctl2);
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H A D | nv50_sor.c | 59 OUT_RING (evo, 0); 61 OUT_RING (evo, 0); 257 OUT_RING(evo, mode_ctl);
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H A D | nouveau_fbcon.c | 175 OUT_RING (chan, 0); 177 OUT_RING (chan, 0); 180 OUT_RING (chan, 0); 182 OUT_RING (chan, 0);
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H A D | nouveau_gem.c | 741 OUT_RING(chan, ((mem->start << PAGE_SHIFT) + 743 OUT_RING(chan, 0); 777 OUT_RING(chan, ((mem->start << PAGE_SHIFT) + 779 OUT_RING(chan, 0); 781 OUT_RING(chan, 0);
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/drivers/gpu/drm/r128/ |
H A D | r128_state.c | 50 OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); 51 OUT_RING(boxes[0].x1); 52 OUT_RING(boxes[0].x2 - 1); 53 OUT_RING(boxes[0].y1); 54 OUT_RING(boxes[0].y2 - 1); 59 OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); 60 OUT_RING(boxes[1].x1); 61 OUT_RING(boxes[1].x2 - 1); 62 OUT_RING(boxes[1].y1); 63 OUT_RING(boxe [all...] |
H A D | r128_drv.h | 463 OUT_RING(CCE_PACKET0(R128_WAIT_UNTIL, 0)); \ 464 OUT_RING(R128_EVENT_CRTC_OFFSET); \ 522 #define OUT_RING(x) do { \ macro 524 DRM_INFO(" OUT_RING( 0x%08x ) at 0x%x\n", \
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/drivers/gpu/drm/radeon/ |
H A D | r600_blit.c | 63 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 64 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); 65 OUT_RING(gpu_addr >> 8); 66 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0)); 67 OUT_RING(2 << 0); 70 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 71 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2); 72 OUT_RING(gpu_addr >> 8); 75 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1)); 76 OUT_RING((R600_CB_COLOR0_SIZ [all...] |
H A D | radeon_state.c | 458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); 459 OUT_RING((box->y1 << 16) | box->x1); 460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); 461 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); 490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); 491 OUT_RING(ctx->pp_misc); 492 OUT_RING(ctx->pp_fog_color); 493 OUT_RING(ctx->re_solid_color); 494 OUT_RING(ctx->rb3d_blendcntl); 495 OUT_RING(ct [all...] |
H A D | r300_cmdbuf.c | 74 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1)); 106 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) | 108 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) | 120 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1)); 121 OUT_RING(0); 122 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK); 147 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 148 OUT_RING(R300_RB3D_DC_FLUSH); 151 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); 152 OUT_RING(RADEON_WAIT_3D_IDLECLEA [all...] |
H A D | radeon_drv.h | 1933 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1934 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1939 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1940 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1945 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1946 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1952 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1953 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1958 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1959 OUT_RING(RADEON_RB3D_DC_FLUS 2106 #define OUT_RING macro [all...] |
H A D | r600_cp.c | 2317 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2318 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2320 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2321 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2322 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2339 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2340 OUT_RING(0x00000001); 2342 OUT_RING(0x00000003); 2344 OUT_RING(0x00000000); 2345 OUT_RING((dev_pri [all...] |
/drivers/gpu/drm/i810/ |
H A D | i810_dma.c | 470 OUT_RING(GFX_OP_COLOR_FACTOR); 471 OUT_RING(code[I810_CTXREG_CF1]); 473 OUT_RING(GFX_OP_STIPPLE); 474 OUT_RING(code[I810_CTXREG_ST1]); 481 OUT_RING(tmp); 488 OUT_RING(0); 502 OUT_RING(GFX_OP_MAP_INFO); 503 OUT_RING(code[I810_TEXREG_MI1]); 504 OUT_RING(code[I810_TEXREG_MI2]); 505 OUT_RING(cod [all...] |
/drivers/gpu/drm/i915/ |
H A D | i915_dma.c | 344 OUT_RING(buffer[i]); 346 OUT_RING(0); 373 OUT_RING(GFX_OP_DRAWRECT_INFO_I965); 374 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); 375 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16)); 376 OUT_RING(DR4); 382 OUT_RING(GFX_OP_DRAWRECT_INFO); 383 OUT_RING(DR1); 384 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16)); 385 OUT_RING(((bo [all...] |
H A D | intel_overlay.c | 316 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON); 317 OUT_RING(overlay->flip_addr | OFC_UPDATE); 318 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); 319 OUT_RING(MI_NOOP); 360 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); 361 OUT_RING(flip_addr); 427 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); 428 OUT_RING(flip_addr); 429 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); 431 OUT_RING(MI_OVERLAY_FLI [all...] |
/drivers/video/intelfb/ |
H A D | intelfbhw.c | 1553 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); 1554 OUT_RING(MI_NOOP); 1691 OUT_RING(br00); 1692 OUT_RING(br13); 1693 OUT_RING(br14); 1694 OUT_RING(br09); 1695 OUT_RING(br16); 1696 OUT_RING(MI_NOOP); 1740 OUT_RING(br00); 1741 OUT_RING(br1 [all...] |