| /drivers/staging/comedi/drivers/ |
| H A D | ni_at_ao.c | 175 unsigned short cfg1; member in struct:atao_private
316 devpriv->cfg1 = 0;
317 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
331 devpriv->cfg1 |= GRP2WR;
332 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
338 devpriv->cfg1 &= ~GRP2WR;
339 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
352 devpriv->cfg1 |= GRP2WR;
353 outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
357 devpriv->cfg1
[all...] |
| /drivers/media/video/ |
| H A D | atmel-isi.c | 372 u32 ctrl, cfg1; local
374 cfg1 = isi_readl(isi, ISI_CFG1);
390 cfg1 |= isi->pdata->frate | ISI_CFG1_DISCR;
395 isi_writel(isi, ISI_CFG1, cfg1);
824 u32 cfg1 = 0; local
879 cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW;
881 cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW;
883 cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING;
886 cfg1 |= ISI_CFG1_EMB_SYNC;
888 cfg1 |
[all...] |
| /drivers/gpu/drm/nouveau/ |
| H A D | nouveau_calc.c | 203 uint32_t cfg1 = nvReadFB(dev, NV04_PFB_CFG1); local
223 sim_data.mem_latency = cfg1 & 0xf;
224 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
|
| /drivers/staging/et131x/ |
| H A D | et131x.c | 957 writel(0xC00F0000, ¯egs->cfg1);
1000 writel(0, ¯egs->cfg1);
1012 u32 cfg1; local
1018 cfg1 = readl(&mac->cfg1);
1034 cfg1 |= CFG1_RX_ENABLE | CFG1_TX_ENABLE | CFG1_TX_FLOW;
1036 cfg1 &= ~(CFG1_LOOPBACK | CFG1_RX_FLOW);
1039 cfg1 |= CFG1_RX_FLOW;
1040 writel(cfg1, &mac->cfg1);
[all...] |
| H A D | et131x.h | 1126 u32 cfg1; /* 0x5000 */ member in struct:mac_regs
|
| /drivers/video/nvidia/ |
| H A D | nv_hw.c | 387 unsigned int MClk, NVClk, cfg1; local
391 cfg1 = NV_RD32(par->PFB, 0x00000204);
397 sim_data.mem_latency = (char)cfg1 & 0x0F;
400 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 31) & 0x01));
626 unsigned int MClk, NVClk, cfg1; local
630 cfg1 = NV_RD32(par->PFB, 0x0204);
637 sim_data.mem_latency = (char)cfg1 & 0x0F;
640 (char)(((cfg1 >> 4) & 0x0F) + ((cfg1 >> 3
[all...] |
| /drivers/video/riva/ |
| H A D | riva_hw.c | 809 unsigned int M, N, P, pll, MClk, NVClk, cfg1; local
817 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
823 sim_data.mem_latency = (char)cfg1 & 0x0F;
825 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01));
1072 unsigned int M, N, P, pll, MClk, NVClk, cfg1; local
1080 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
1088 sim_data.mem_latency = (char)cfg1 & 0x0F;
1090 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 3
[all...] |
| /drivers/scsi/ |
| H A D | qla1280.c | 2226 uint16_t hwrev, cfg1, cdma_conf, ddma_conf; local
2230 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6);
2236 cfg1 |= nv->isp_config.fifo_threshold << 4;
2238 cfg1 |= nv->isp_config.burst_enable << 2;
2239 WRT_REG_WORD(®->cfg_1, cfg1);
2244 uint16_t cfg1, term; local
2247 cfg1 = nv->isp_config.fifo_threshold << 4;
2248 cfg1 |= nv->isp_config.burst_enable << 2;
2251 cfg1 |= BIT_13;
2252 WRT_REG_WORD(®->cfg_1, cfg1);
[all...] |
| /drivers/net/ethernet/smsc/ |
| H A D | smc91x.c | 913 int bmcr, cfg1; local
918 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
919 cfg1 |= PHY_CFG1_LNKDIS;
920 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
|
| /drivers/net/ethernet/realtek/ |
| H A D | r8169.c | 5007 u8 cfg1; local
5019 cfg1 = RTL_R8(Config1);
5020 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5021 RTL_W8(Config1, cfg1 & ~LEDS0);
|