Searched refs:crtc1 (Results 1 - 6 of 6) sorted by relevance

/drivers/video/matrox/
H A Dmatroxfb_base.c181 if (minfo->crtc1.panpos >= 0) {
186 panpos = minfo->crtc1.panpos;
190 minfo->crtc1.panpos = -1; /* No update pending anymore */
211 minfo->crtc1.vsync.cnt++;
213 wake_up_interruptible(&minfo->crtc1.vsync.wait);
276 vs = &minfo->crtc1.vsync;
342 minfo->crtc1.panpos = p2;
345 minfo->crtc1.panpos = -1;
814 minfo->crtc1.pixclock = mt.pixclock;
815 minfo->crtc1
[all...]
H A Dmatroxfb_DAC1064.c175 pixelmnp = minfo->crtc1.mnp;
211 pxc = minfo->crtc1.pixclock;
814 /* stop crtc1 */
825 /* restore crtc1 */
1056 minfo->crtc1.panpos = -1;
1082 minfo->crtc1.panpos = -1;
H A Dmatroxfb_base.h380 } crtc1; member in struct:matrox_fb_info
H A Dmatroxfb_Ti3026.c583 minfo->crtc1.panpos = -1;
/drivers/gpu/drm/nouveau/
H A Dnvd0_display.c1699 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800)); local
1702 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
/drivers/gpu/drm/radeon/
H A Devergreen.c2532 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; local
2581 crtc1 |= VBLANK_INT_MASK;
2645 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);

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