/drivers/staging/comedi/drivers/addi-data/ |
H A D | hwdrv_apci3120.c | 86 devpriv->ui_EocEosConversionTime = data[2]; 94 devpriv->s_EeParameters.i_NbrAiChannel) { 100 devpriv->b_InterruptMode = APCI3120_EOS_MODE; 103 devpriv->b_EocEosInterrupt = APCI3120_ENABLE; 105 devpriv->b_EocEosInterrupt = APCI3120_DISABLE; 106 /* Copy channel list and Range List to devpriv */ 108 devpriv->ui_AiNbrofChannels = data[3]; 109 for (i = 0; i < devpriv->ui_AiNbrofChannels; i++) 110 devpriv->ui_AiChannelList[i] = data[4 + i]; 113 devpriv [all...] |
H A D | hwdrv_apci1500.c | 153 devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER); 157 outb(0x00, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER); 280 devpriv->iobase + 286 devpriv->iobase + 292 devpriv->iobase + 295 devpriv->iobase + 303 devpriv->iobase + 306 devpriv->iobase + 313 devpriv->iobase + 316 devpriv [all...] |
H A D | hwdrv_APCI1710.c | 211 ret = inl(devpriv->s_BoardInfos.ui_Address + 60); 212 devpriv->s_BoardInfos.dw_MolduleConfiguration[0] = ret; 214 ret = inl(devpriv->s_BoardInfos.ui_Address + 124); 215 devpriv->s_BoardInfos.dw_MolduleConfiguration[1] = ret; 217 ret = inl(devpriv->s_BoardInfos.ui_Address + 188); 218 devpriv->s_BoardInfos.dw_MolduleConfiguration[2] = ret; 220 ret = inl(devpriv->s_BoardInfos.ui_Address + 252); 221 devpriv->s_BoardInfos.dw_MolduleConfiguration[3] = ret; 223 /* outl(0x80808082,devpriv->s_BoardInfos.ui_Address+0x60); */ 224 outl(0x83838383, devpriv [all...] |
H A D | hwdrv_apci1564.c | 92 devpriv->tsk_Current = current; 100 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP + 103 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP + 107 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP + 112 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP + 118 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP + 121 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP + 124 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP + 159 (unsigned int) inl(devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP); 201 *data = (unsigned int) inl(devpriv [all...] |
H A D | hwdrv_apci035.c | 119 devpriv->tsk_Current = current; 120 devpriv->b_TimerSelectMode = data[0]; 127 /* ui_Command = inl(devpriv->iobase+((i_WatchdogNbr-1)*32)+12); */ 130 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); 132 ui_Command = inl(devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); 136 outl(data[3], devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 4); 140 outl(data[2], devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 8); 176 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); 178 ui_Command = inl(devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12); 189 outl(ui_Command, devpriv [all...] |
H A D | APCI1710_Inp_cpt.c | 155 if ((devpriv->s_BoardInfos. 179 inl(devpriv-> 190 devpriv-> 200 devpriv-> 205 (devpriv-> 222 devpriv-> 228 devpriv-> 240 devpriv-> 246 (devpriv-> 260 devpriv [all...] |
H A D | hwdrv_apci3xxx.c | 72 if ((readl(devpriv->dw_AiBase + 8) & 0x80000UL) == 0x80000UL) 167 devpriv->s_EeParameters. 173 && (devpriv->s_EeParameters.i_NbrAiChannel == 0)) 189 devpriv-> 194 devpriv-> 198 devpriv-> 202 devpriv-> 211 devpriv->dw_AiBase + 36); 217 writel(dw_ReloadValue, devpriv->dw_AiBase + 32); 373 if (devpriv [all...] |
H A D | hwdrv_apci1032.c | 94 devpriv->tsk_Current = current; 103 devpriv->iobase + APCI1032_DIGITAL_IP_INTERRUPT_MODE1); 105 devpriv->iobase + APCI1032_DIGITAL_IP_INTERRUPT_MODE2); 107 outl(0x4, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ); 109 inl(devpriv->iobase + APCI1032_DIGITAL_IP_IRQ); 112 outl(0x6, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ); 119 devpriv->iobase + APCI1032_DIGITAL_IP_INTERRUPT_MODE1); 121 devpriv->iobase + APCI1032_DIGITAL_IP_INTERRUPT_MODE2); 122 outl(0x0, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ); 154 ui_TmpValue = (unsigned int) inl(devpriv [all...] |
H A D | APCI1710_INCCPT.c | 87 devpriv->tsk_Current = current; /* Save the current process task structure */ 315 if ((devpriv->s_BoardInfos. 440 devpriv-> 449 devpriv-> 465 devpriv-> 470 b_ModeRegister1 = devpriv-> 484 outl(devpriv->s_ModuleInfo[b_ModulNbr]. 488 devpriv->s_BoardInfos. 491 devpriv-> 560 if ((devpriv [all...] |
H A D | APCI1710_82x54.c | 253 if ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF0000UL) == APCI1710_82X54_TIMER) { 276 ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0x0000FFFFUL) >= 0x3131)) || 289 if ((b_InputClockSelection == APCI1710_10MHZ) && ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0x0000FFFFUL) > 0x3131)) { 291 dw_Test = inl(devpriv->s_BoardInfos.ui_Address + (16 + (b_TimerNbr * 4) + (64 * b_ModulNbr))); 302 devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_82X54Init = 1; 305 devpriv-> s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_InputClockSelection = b_InputClockSelection; 308 devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_InputClockLevel = ~b_InputClockLevel & 1; 311 devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_OutputLevel = ~b_OutputLevel & 1; 314 devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_HardwareGateLevel = b_HardwareGateLevel; 319 devpriv [all...] |
H A D | hwdrv_apci3501.c | 83 *data = inl(devpriv->iobase + APCI3501_DIGITAL_IP); 134 devpriv->b_OutputMemoryStatus = ADDIDATA_ENABLE; 137 devpriv->b_OutputMemoryStatus = ADDIDATA_DISABLE; 169 if (devpriv->b_OutputMemoryStatus) { 170 ui_Temp = inl(devpriv->iobase + APCI3501_DIGITAL_OP); 171 } /* if(devpriv->b_OutputMemoryStatus ) */ 174 } /* if(devpriv->b_OutputMemoryStatus ) */ 178 outl(data[0], devpriv->iobase + APCI3501_DIGITAL_OP); 184 devpriv->iobase + APCI3501_DIGITAL_OP); 203 devpriv [all...] |
H A D | APCI1710_Dig_io.c | 135 devpriv->s_ModuleInfo[b_ModulNbr]. 141 devpriv->s_ModuleInfo[b_ModulNbr]. 149 devpriv->s_ModuleInfo[b_ModulNbr]. 160 if ((devpriv->s_BoardInfos. 175 devpriv->s_ModuleInfo[b_ModulNbr]. 183 devpriv->s_ModuleInfo[b_ModulNbr]. 191 devpriv->s_ModuleInfo[b_ModulNbr]. 208 devpriv->s_BoardInfos. 318 if ((devpriv->s_BoardInfos. 330 if (devpriv [all...] |
H A D | APCI1710_Ttl.c | 127 if ((devpriv->s_BoardInfos. 133 devpriv->s_ModuleInfo[b_ModulNbr]. 140 devpriv->s_ModuleInfo[b_ModulNbr]. 147 devpriv->s_ModuleInfo[b_ModulNbr]. 154 devpriv->s_ModuleInfo[b_ModulNbr]. 161 devpriv->s_ModuleInfo[b_ModulNbr]. 169 devpriv->s_BoardInfos.ui_Address + 20 + 184 if ((devpriv->s_BoardInfos. 212 devpriv-> 224 devpriv [all...] |
H A D | APCI1710_Ssi.c | 149 if ((devpriv->s_BoardInfos. 197 devpriv-> 205 devpriv-> 213 devpriv-> 227 outl(b_SSIProfile + 1, devpriv->s_BoardInfos.ui_Address + 4 + (64 * b_ModulNbr)); 230 outl(b_SSIProfile, devpriv->s_BoardInfos.ui_Address + 4 + (64 * b_ModulNbr)); 247 outl(ui_TimerValue, devpriv->s_BoardInfos.ui_Address + (64 * b_ModulNbr)); 253 outl(7 * b_SSICountingMode, devpriv->s_BoardInfos.ui_Address + 12 + (64 * b_ModulNbr)); 255 devpriv-> 430 if ((devpriv [all...] |
H A D | hwdrv_apci2016.c | 87 devpriv->b_OutputMemoryStatus = ADDIDATA_ENABLE; 90 devpriv->b_OutputMemoryStatus = ADDIDATA_DISABLE; 125 if (devpriv->b_OutputMemoryStatus) { 126 ui_Temp = inw(devpriv->iobase + APCI2016_DIGITAL_OP); 127 } /* if (devpriv->b_OutputMemoryStatus ) */ 130 } /* else if (devpriv->b_OutputMemoryStatus ) */ 140 outw(data[0], devpriv->iobase + APCI2016_DIGITAL_OP); 168 devpriv->iobase + APCI2016_DIGITAL_OP); 185 devpriv->iobase + APCI2016_DIGITAL_OP); 234 devpriv [all...] |
/drivers/staging/comedi/drivers/ |
H A D | adl_pci9118.c | 440 #define devpriv ((struct pci9118_private *)dev->private) macro 479 devpriv->AdControlReg = AdControl_Int & 0xff; 480 devpriv->AdFunctionReg = AdFunction_PDTrg | AdFunction_PETrg; 481 outl(devpriv->AdFunctionReg, dev->iobase + PCI9118_ADFUNC); 511 if (devpriv->ai16bits) { 544 devpriv->ao_data[ch] = data[n]; 561 data[n] = devpriv->ao_data[chan]; 600 devpriv->AdFunctionReg = 602 outl(devpriv->AdFunctionReg, dev->iobase + PCI9118_ADFUNC); 604 outl((devpriv [all...] |
H A D | ni_labpc.c | 496 #define devpriv ((struct labpc_private *)dev->private) macro 565 devpriv->read_byte = labpc_readb; 566 devpriv->write_byte = labpc_writeb; 568 devpriv->read_byte = labpc_inb; 569 devpriv->write_byte = labpc_outb; 572 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); 573 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); 574 devpriv [all...] |
H A D | pcl818.c | 382 #define devpriv ((struct pcl818_private *)dev->private) macro 467 data[n] = devpriv->ao_readback[chan]; 480 devpriv->ao_readback[chan] = data[n]; 562 if ((low & 0xf) != devpriv->act_chanlist[devpriv->act_chanlist_pos]) { /* dropout! */ 566 devpriv->act_chanlist[devpriv->act_chanlist_pos]); 572 devpriv->act_chanlist_pos++; 573 if (devpriv->act_chanlist_pos >= devpriv [all...] |
H A D | pcl816.c | 150 #define devpriv ((struct pcl816_private *)dev->private) macro 339 if (++devpriv->ai_act_chanlist_pos >= devpriv->ai_act_chanlist_len) 340 devpriv->ai_act_chanlist_pos = 0; 343 if (s->async->cur_chan >= devpriv->ai_n_chan) { 345 devpriv->ai_act_scan++; 348 if (!devpriv->ai_neverending) 350 if (devpriv->ai_act_scan >= devpriv->ai_scans) { 375 if (++devpriv [all...] |
H A D | pcl812.c | 461 #define devpriv ((struct pcl812_private *)dev->private) macro 484 outb(devpriv->mode_reg_int | 1, dev->iobase + PCL812_MODE); 501 outb(devpriv->mode_reg_int | 0, dev->iobase + PCL812_MODE); 507 outb(devpriv->mode_reg_int | 0, dev->iobase + PCL812_MODE); 565 devpriv->ao_readback[chan] = data[i]; 582 data[i] = devpriv->ao_readback[chan]; 668 if (devpriv->use_ext_trg) 711 if (devpriv->use_ext_trg) { 840 if (devpriv->use_ext_trg) { 865 devpriv [all...] |
H A D | rtd520.c | 411 #define devpriv ((struct rtdPrivate *)dev->private) macro 417 writel(0, devpriv->las0+LAS0_BOARD_RESET) 421 writel(0, devpriv->las0+LAS0_CGT_RESET) 425 writel(0, devpriv->las0+LAS0_CGT_CLEAR) 429 writel((v > 0) ? 1 : 0, devpriv->las0+LAS0_CGT_ENABLE) 433 writel(v, devpriv->las0+LAS0_CGT_WRITE) 437 writel(v, devpriv->las0+LAS0_CGL_WRITE) 441 writel(0, devpriv->las0+LAS0_ADC_FIFO_CLEAR) 445 writel(v, devpriv->las0+LAS0_ADC_CONVERSION) 449 writel(v, devpriv [all...] |
H A D | icp_multi.c | 220 #define devpriv ((struct icp_multi_private *)dev->private) macro 273 devpriv->IntEnable &= ~ADC_READY; 274 writew(devpriv->IntEnable, devpriv->io_addr + ICP_MULTI_INT_EN); 277 devpriv->IntStatus |= ADC_READY; 278 writew(devpriv->IntStatus, devpriv->io_addr + ICP_MULTI_INT_STAT); 285 readw(devpriv->io_addr + ICP_MULTI_ADC_CSR), 286 devpriv->io_addr + ICP_MULTI_ADC_CSR); 291 devpriv [all...] |
H A D | cb_pcimdas.c | 173 #define devpriv ((struct cb_pcimdas_private *)dev->private) macro 242 devpriv->pci_dev = pcidev; 271 devpriv->BADR0 = pci_resource_start(devpriv->pci_dev, 0); 272 devpriv->BADR1 = pci_resource_start(devpriv->pci_dev, 1); 273 devpriv->BADR2 = pci_resource_start(devpriv->pci_dev, 2); 274 devpriv->BADR3 = pci_resource_start(devpriv [all...] |
H A D | ni_mio_common.c | 415 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); 418 devpriv->int_a_enable_reg &= ~bit_mask; 419 devpriv->int_a_enable_reg |= bit_values & bit_mask; 420 devpriv->stc_writew(dev, devpriv->int_a_enable_reg, 424 devpriv->int_b_enable_reg &= ~bit_mask; 425 devpriv->int_b_enable_reg |= bit_values & bit_mask; 426 devpriv->stc_writew(dev, devpriv->int_b_enable_reg, 430 devpriv [all...] |
H A D | amplc_pci224.c | 422 #define devpriv ((struct pci224_private *)dev->private) macro 493 devpriv->ao_readback[chan] = data; 497 devpriv->daccon = COMBINE(devpriv->daccon, devpriv->hwrange[range], 500 outw(devpriv->daccon | PCI224_DACCON_FIFORESET, 508 if ((devpriv->daccon & PCI224_DACCON_POLAR_MASK) == 558 data[i] = devpriv->ao_readback[chan]; 582 if (!test_and_clear_bit(AO_CMD_STARTED, &devpriv->state)) 586 spin_lock_irqsave(&devpriv [all...] |