Searched refs:hsync_start (Results 1 - 25 of 37) sorted by relevance

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/drivers/staging/omapdrm/
H A Domap_connector.c42 mode->hsync_start = mode->hdisplay + timings->hfp;
43 mode->hsync_end = mode->hsync_start + timings->hsw;
66 timings->hfp = mode->hsync_start - mode->hdisplay;
67 timings->hsw = mode->hsync_end - mode->hsync_start;
234 mode->hdisplay, mode->hsync_start,
301 mode->hdisplay, mode->hsync_start,
/drivers/gpu/drm/exynos/
H A Dexynos_drm_connector.c57 mode->hsync_start = mode->hdisplay + timing->left_margin;
58 mode->hsync_end = mode->hsync_start + timing->hsync_len;
88 timing->left_margin = mode->hsync_start - mode->hdisplay;
89 timing->hsync_len = mode->hsync_end - mode->hsync_start;
/drivers/gpu/drm/radeon/
H A Dradeon_encoders.c269 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
271 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
283 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
284 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
H A Dradeon_legacy_crtc.c56 int hsync_start; local
86 hsync_start = mode->crtc_hsync_start - 8;
88 fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
545 int hsync_start; local
592 hsync_start = mode->crtc_hsync_start - 8;
594 crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
/drivers/gpu/drm/
H A Ddrm_modes.c55 mode->hdisplay, mode->hsync_start,
220 drm_mode->hsync_start = drm_mode->hsync_end -
222 drm_mode->hsync_start += CVT_H_GRANULARITY -
223 drm_mode->hsync_start % CVT_H_GRANULARITY;
255 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC;
443 drm_mode->hsync_start = hdisplay_rnd + hfront_porch;
444 drm_mode->hsync_end = drm_mode->hsync_start + hsync;
673 p->crtc_hsync_start = p->hsync_start;
770 mode1->hsync_start == mode2->hsync_start
[all...]
H A Ddrm_edid.c724 mode->hsync_start = mode->hsync_start - 1;
863 mode->hsync_start = mode->hdisplay + hsync_offset;
864 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
912 (mode->hsync_end - mode->hsync_start == 32) &&
H A Ddrm_crtc.c1070 out->hsync_start = in->hsync_start;
1102 out->hsync_start = in->hsync_start;
/drivers/gpu/drm/gma500/
H A Dintel_bios.c60 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
62 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
H A Doaktrail_lvds.c267 mode->hsync_start = mode->hdisplay + \
270 mode->hsync_end = mode->hsync_start + \
287 printk(KERN_INFO "HSS is %d\n", mode->hsync_start);
H A Dcdv_intel_lvds.c299 adjusted_mode->hsync_start = panel_fixed_mode->hsync_start;
H A Dpsb_drv.c522 mode->hsync_start = umode->hsync_start;
H A Dpsb_intel_lvds.c422 adjusted_mode->hsync_start = panel_fixed_mode->hsync_start;
/drivers/gpu/drm/i915/
H A Dintel_panel.c40 adjusted_mode->hsync_start = fixed_mode->hsync_start;
H A Dintel_bios.c81 panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay +
83 panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start +
H A Dintel_dvo.c152 C(hsync_start);
H A Dintel_tv.c1092 .hsync_start = 1368,
1339 mode_ptr->hsync_start = hactive_s + 1;
1341 if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
1342 mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
H A Dintel_lvds.c771 scan->hsync_start == fixed_mode->hsync_start &&
/drivers/video/vermilion/
H A Dvermilion.c784 u32 htotal, hactive, hblank_start, hblank_end, hsync_start, hsync_end; local
801 hsync_start = hactive + var->right_margin;
802 hsync_end = hsync_start + var->hsync_len;
850 ((hsync_end - 1) << 16) | (hsync_start - 1));
/drivers/video/
H A Dgbefb.c533 timing->hsync_start = var->xres + var->right_margin + 1;
534 timing->hsync_end = timing->hsync_start + var->hsync_len;
569 SET_GBE_FIELD(VT_HSYNC, HSYNC_ON, val, timing->hsync_start);
998 var->right_margin = timing.hsync_start - timing.width;
1001 var->hsync_len = timing.hsync_end - timing.hsync_start;
H A Dsgivwfb.c344 var->right_margin = timing->hsync_start - timing->width;
347 var->hsync_len = timing->hsync_end - timing->hsync_start;
534 currentTiming->hsync_start);
/drivers/gpu/drm/nouveau/
H A Dnv04_dfp.c302 (output_mode->hsync_start - output_mode->hdisplay) >=
306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - dev_priv->vbios.digital_min_front_porch - 1;
307 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
H A Dnv17_tv.c269 mode->hsync_start = (mode->hdisplay + (mode->htotal
271 mode->hsync_end = mode->hsync_start + 8;
530 output_mode->hsync_start - 1;
H A Dnv50_crtc.c622 hsynce = mode->hsync_end - mode->hsync_start - 1;
625 hfrontp = mode->hsync_start - mode->hdisplay;
/drivers/video/intelfb/
H A Dintelfbhw.c1050 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive; local
1177 hsync_start = hactive + var->right_margin;
1178 hsync_end = hsync_start + var->hsync_len;
1184 hactive, hsync_start, hsync_end, htotal, hblank_start,
1205 hsync_start--;
1206 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1243 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
/drivers/gpu/drm/i2c/
H A Dch7006_drv.c141 start_active = (drm_mode->htotal & ~0x7) - (drm_mode->hsync_start & ~0x7);

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