Searched refs:pllvals (Results 1 - 6 of 6) sorted by relevance
/drivers/gpu/drm/nouveau/ |
H A D | nouveau_hw.c | 395 uint32_t pll2, struct nouveau_pll_vals *pllvals) 402 pllvals->log2P = (pll1 >> 16) & 0x7; 403 pllvals->N2 = pllvals->M2 = 1; 406 pllvals->NM1 = pll2 & 0xffff; 409 pllvals->NM2 = pll2 >> 16; 411 pllvals->NM1 = pll1 & 0xffff; 413 pllvals->NM2 = pll2 & 0xffff; 415 pllvals->M1 &= 0xf; /* only 4 bits */ 417 pllvals 394 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, uint32_t pll2, struct nouveau_pll_vals *pllvals) argument 426 nouveau_hw_get_pllvals(struct drm_device *dev, enum pll_types plltype, struct nouveau_pll_vals *pllvals) argument 483 struct nouveau_pll_vals pllvals; local [all...] |
H A D | nouveau_hw.h | 44 struct nouveau_pll_vals *pllvals); 45 int nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pllvals);
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H A D | nv04_dfp.c | 602 (&dev_priv->saved_reg.crtc_reg[head].pllvals);
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H A D | nv04_crtc.c | 110 struct nouveau_pll_vals *pv = ®p->pllvals;
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H A D | nouveau_bios.c | 678 struct nouveau_pll_vals pllvals; local 689 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals); 695 nouveau_hw_setpll(dev, reg, &pllvals);
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H A D | nouveau_drv.h | 632 struct nouveau_pll_vals pllvals; member in struct:nv04_crtc_reg
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