/drivers/media/video/ |
H A D | imx074.c | 103 static int reg_write(struct i2c_client *client, const u16 addr, const u8 data) function 251 return reg_write(client, MODE_SELECT, !!enable); 326 reg_write(client, PLL_MULTIPLIER, 0x2D); 327 reg_write(client, PRE_PLL_CLK_DIV, 0x02); 328 reg_write(client, PLSTATIM, 0x4B); 331 reg_write(client, 0x3024, 0x00); 333 reg_write(client, IMAGE_ORIENTATION, 0x00); 340 reg_write(client, 0x0112, 0x08); 341 reg_write(client, 0x0113, 0x08); 344 reg_write(clien [all...] |
H A D | rj54n1cb0c.c | 443 static int reg_write(struct i2c_client *client, const u16 reg, function 469 return reg_write(client, reg, (ret & ~mask) | (data & mask)); 478 ret = reg_write(client, rv->reg, rv->val); 511 ret = reg_write(client, reg_xy, 516 ret = reg_write(client, reg_x, width & 0xff); 518 ret = reg_write(client, reg_y, height & 0xff); 529 int ret = reg_write(client, RJ54N1_INIT_START, 1); 532 ret = reg_write(client, RJ54N1_INIT_START, 0); 711 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff); 713 ret = reg_write(clien [all...] |
H A D | mt9m001.c | 115 static int reg_write(struct i2c_client *client, const u8 reg, function 129 return reg_write(client, reg, ret | data); 140 return reg_write(client, reg, ret & ~data); 153 ret = reg_write(client, MT9M001_RESET, 1); 155 ret = reg_write(client, MT9M001_RESET, 0); 159 ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 0); 169 if (reg_write(client, MT9M001_OUTPUT_CONTROL, enable ? 2 : 0) < 0) 202 ret = reg_write(client, MT9M001_HORIZONTAL_BLANKING, hblank); 204 ret = reg_write(client, MT9M001_VERTICAL_BLANKING, vblank); 211 ret = reg_write(clien [all...] |
H A D | mt9v022.c | 136 static int reg_write(struct i2c_client *client, const u8 reg, function 150 return reg_write(client, reg, ret | data); 161 return reg_write(client, reg, ret & ~data); 175 ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control); 177 ret = reg_write(client, MT9V022_READ_MODE, 0x300); 184 ret = reg_write(client, MT9V022_ANALOG_GAIN, 16); 186 ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, 480); 188 ret = reg_write(client, MT9V022_MAX_TOTAL_SHUTTER_WIDTH, 480); 193 ret = reg_write(client, MT9V022_DIGITAL_TEST_PATTERN, 0); 212 if (reg_write(clien [all...] |
H A D | mt9t031.c | 96 static int reg_write(struct i2c_client *client, const u8 reg, function 110 return reg_write(client, reg, ret | data); 121 return reg_write(client, reg, ret & ~data); 128 ret = reg_write(client, MT9T031_SHUTTER_WIDTH_UPPER, data >> 16); 131 ret = reg_write(client, MT9T031_SHUTTER_WIDTH, data & 0xffff); 155 ret = reg_write(client, MT9T031_RESET, 1); 157 ret = reg_write(client, MT9T031_RESET, 0); 257 ret = reg_write(client, MT9T031_HORIZONTAL_BLANKING, hblank); 259 ret = reg_write(client, MT9T031_VERTICAL_BLANKING, vblank); 264 ret = reg_write(clien [all...] |
H A D | ak881x.c | 45 static int reg_write(struct i2c_client *client, const u8 reg, function 57 return reg_write(client, reg, (ret & ~mask) | (data & mask)); 114 if (reg_write(client, reg->reg, reg->val) < 0) 218 reg_write(client, AK881X_DAC_MODE, dac); 223 reg_write(client, AK881X_DAC_MODE, 0); 317 reg_write(client, AK881X_INTERFACE_MODE, ifmode | (20 << 3));
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H A D | mt9m111.c | 131 #define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val)) macro 316 return reg_write(CONTEXT_CONTROL, ctx->control); 340 ret = reg_write(COLUMN_START, rect->left); 342 ret = reg_write(ROW_START, rect->top); 345 ret = reg_write(WINDOW_WIDTH, rect->width); 347 ret = reg_write(WINDOW_HEIGHT, rect->height); 369 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE); 701 return reg_write(GLOBAL_GAIN, val);
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H A D | ov5642.c | 663 static int reg_write(struct i2c_client *client, u16 reg, u8 val) function 686 ret = reg_write(client, reg, val16 >> 8); 689 return reg_write(client, reg + 1, val16 & 0x00ff); 718 return reg_write(client, reg->reg, reg->val); 726 int ret = reg_write(client, vals->reg_num, vals->value);
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/drivers/firewire/ |
H A D | init_ohci1394_dma.c | 53 static inline void reg_write(const struct ohci *ohci, int offset, u32 data) function 71 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); 88 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); 102 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); 127 reg_write(ohci, OHCI1394_BusOptions, bus_options); 130 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); 133 reg_write(ohci, OHCI1394_HCControlSet, 137 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); 140 reg_write(ohci, OHCI1394_LinkControlSet, 144 reg_write(ohc [all...] |
H A D | nosy.c | 226 reg_write(struct pcilynx *lynx, int offset, u32 data) function 240 reg_write(lynx, offset, (reg_read(lynx, offset) | mask)); 251 reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20, pcl_bus); 252 reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20, 269 reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | 479 reg_write(lynx, LINK_INT_STATUS, link_int_status); 489 reg_write(lynx, PCI_INT_STATUS, pci_int_status); 510 reg_write(lynx, PCI_INT_ENABLE, 0); 598 reg_write(lynx, DMA0_CHAN_CTRL, 0); 599 reg_write(lyn [all...] |
H A D | ohci.c | 519 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) function 546 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); 571 reg_write(ohci, OHCI1394_PhyControl, 662 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); 684 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); 1032 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); 1033 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); 1204 reg_write(ohci, COMMAND_PTR(ctx->regs), 1206 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); 1207 reg_write(ohc [all...] |
/drivers/i2c/busses/ |
H A D | i2c-pasemi.c | 64 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) function 80 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg)) 88 reg_write(smbus, REG_SMSTA, status); 109 reg_write(smbus, REG_SMSTA, status); 114 reg_write(smbus, REG_SMSTA, SMSTA_XEN); 157 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | 324 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | 377 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR |
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/drivers/media/video/gspca/ |
H A D | spca505.c | 570 static int reg_write(struct usb_device *dev, function 614 ret = reg_write(dev, data[i][0], data[i][2], data[i][1]); 659 reg_write(gspca_dev->dev, 0x05, 0x00, (255 - brightness) >> 6); 660 reg_write(gspca_dev->dev, 0x05, 0x01, (255 - brightness) << 2); 694 ret = reg_write(gspca_dev->dev, 0x06, 0x16, 0x0a); 697 reg_write(gspca_dev->dev, 0x05, 0xc2, 0x12); 702 reg_write(dev, 0x02, 0x00, 0x00); 705 reg_write(dev, SPCA50X_REG_COMPRESS, 0x00, mode_tb[mode][0]); 706 reg_write(dev, SPCA50X_REG_COMPRESS, 0x06, mode_tb[mode][1]); 707 reg_write(de [all...] |
H A D | spca508.c | 1267 static int reg_write(struct usb_device *dev, function 1315 ret = reg_write(dev, 0x8802, reg >> 8); 1318 ret = reg_write(dev, 0x8801, reg & 0x00ff); 1322 ret = reg_write(dev, 0x8805, val & 0x00ff); 1327 ret = reg_write(dev, 0x8800, val); 1363 ret = reg_write(dev, (*data)[1], (*data)[0]); 1431 reg_write(gspca_dev->dev, 0x8500, mode); 1435 reg_write(gspca_dev->dev, 0x8700, 0x28); /* clock */ 1440 reg_write(gspca_dev->dev, 0x8700, 0x23); /* clock */ 1443 reg_write(gspca_de [all...] |
H A D | spca501.c | 1844 static int reg_write(struct usb_device *dev, function 1869 ret = reg_write(dev, data[i][0], data[i][2], data[i][1]); 1885 reg_write(gspca_dev->dev, SPCA501_REG_CCDSP, 0x12, sd->brightness); 1892 reg_write(gspca_dev->dev, 0x00, 0x00, 1894 reg_write(gspca_dev->dev, 0x00, 0x01, 1902 reg_write(gspca_dev->dev, SPCA501_REG_CCDSP, 0x0c, sd->colors); 1909 reg_write(gspca_dev->dev, SPCA501_REG_CCDSP, 0x11, sd->blue_balance); 1916 reg_write(gspca_dev->dev, SPCA501_REG_CCDSP, 0x13, sd->red_balance); 1996 reg_write(dev, SPCA50X_REG_USB, 0x6, 0x94); 1999 reg_write(de [all...] |
/drivers/net/dsa/ |
H A D | mv88e6060.c | 36 static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) function 46 __ret = reg_write(ds, addr, reg, val); \ 218 return reg_write(ds, addr, regnum, val);
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/drivers/gpu/drm/radeon/ |
H A D | atom.h | 114 void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ member in struct:card_info
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H A D | atom.c | 469 gctx->card->reg_write(gctx->card, idx, 472 gctx->card->reg_write(gctx->card, idx, val);
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H A D | radeon_device.c | 545 atom_card_info->reg_write = cail_reg_write;
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/drivers/atm/ |
H A D | lanai.c | 487 static inline void reg_write(const struct lanai_dev *lanai, u32 val, function 497 reg_write(lanai, lanai->conf1, Config1_Reg); 502 reg_write(lanai, lanai->conf2, Config2_Reg); 518 reg_write(lanai, 0, Reset_Reg); 1071 reg_write(lanai, i, IntControlEna_Reg); 1076 reg_write(lanai, i, IntControlDis_Reg); 1282 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg); 1582 reg_write(lanai, INT_ALL, IntAck_Reg); 1602 reg_write(lanai, 0, ServWrite_Reg); 1604 reg_write(lana [all...] |
/drivers/mfd/ |
H A D | mcp-sa11x0.c | 134 .reg_write = mcp_sa11x0_write,
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H A D | mcp-core.c | 135 mcp->ops->reg_write(mcp, reg, val);
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/drivers/net/ethernet/smsc/ |
H A D | smsc911x.c | 85 void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val); member in struct:smsc911x_ops 235 pdata->ops->reg_write(pdata, reg, val); 2275 .reg_write = __smsc911x_reg_write, 2283 .reg_write = __smsc911x_reg_write_shift,
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/drivers/video/ |
H A D | w100fb.c | 139 static DEVICE_ATTR(reg_write, 0200, NULL, w100fb_reg_write);
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