1/* 2 * pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer 3 * (C) 2005 Red Hat Inc 4 * Alan Cox <alan@lxorguk.ukuu.org.uk> 5 * (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz 6 * 7 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c 8 * 9 * First cut with LBA48/ATAPI 10 * 11 * TODO: 12 * Channel interlock/reset on both required ? 13 */ 14 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/pci.h> 18#include <linux/init.h> 19#include <linux/blkdev.h> 20#include <linux/delay.h> 21#include <scsi/scsi_host.h> 22#include <linux/libata.h> 23 24#define DRV_NAME "pata_pdc202xx_old" 25#define DRV_VERSION "0.4.3" 26 27static int pdc2026x_cable_detect(struct ata_port *ap) 28{ 29 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 30 u16 cis; 31 32 pci_read_config_word(pdev, 0x50, &cis); 33 if (cis & (1 << (10 + ap->port_no))) 34 return ATA_CBL_PATA40; 35 return ATA_CBL_PATA80; 36} 37 38static void pdc202xx_exec_command(struct ata_port *ap, 39 const struct ata_taskfile *tf) 40{ 41 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); 42 43 iowrite8(tf->command, ap->ioaddr.command_addr); 44 ndelay(400); 45} 46 47static bool pdc202xx_irq_check(struct ata_port *ap) 48{ 49 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 50 unsigned long master = pci_resource_start(pdev, 4); 51 u8 sc1d = inb(master + 0x1d); 52 53 if (ap->port_no) { 54 /* 55 * bit 7: error, bit 6: interrupting, 56 * bit 5: FIFO full, bit 4: FIFO empty 57 */ 58 return sc1d & 0x40; 59 } else { 60 /* 61 * bit 3: error, bit 2: interrupting, 62 * bit 1: FIFO full, bit 0: FIFO empty 63 */ 64 return sc1d & 0x04; 65 } 66} 67 68/** 69 * pdc202xx_configure_piomode - set chip PIO timing 70 * @ap: ATA interface 71 * @adev: ATA device 72 * @pio: PIO mode 73 * 74 * Called to do the PIO mode setup. Our timing registers are shared 75 * so a configure_dmamode call will undo any work we do here and vice 76 * versa 77 */ 78 79static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio) 80{ 81 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 82 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; 83 static u16 pio_timing[5] = { 84 0x0913, 0x050C , 0x0308, 0x0206, 0x0104 85 }; 86 u8 r_ap, r_bp; 87 88 pci_read_config_byte(pdev, port, &r_ap); 89 pci_read_config_byte(pdev, port + 1, &r_bp); 90 r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */ 91 r_bp &= ~0x1F; 92 r_ap |= (pio_timing[pio] >> 8); 93 r_bp |= (pio_timing[pio] & 0xFF); 94 95 if (ata_pio_need_iordy(adev)) 96 r_ap |= 0x20; /* IORDY enable */ 97 if (adev->class == ATA_DEV_ATA) 98 r_ap |= 0x10; /* FIFO enable */ 99 pci_write_config_byte(pdev, port, r_ap); 100 pci_write_config_byte(pdev, port + 1, r_bp); 101} 102 103/** 104 * pdc202xx_set_piomode - set initial PIO mode data 105 * @ap: ATA interface 106 * @adev: ATA device 107 * 108 * Called to do the PIO mode setup. Our timing registers are shared 109 * but we want to set the PIO timing by default. 110 */ 111 112static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev) 113{ 114 pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); 115} 116 117/** 118 * pdc202xx_configure_dmamode - set DMA mode in chip 119 * @ap: ATA interface 120 * @adev: ATA device 121 * 122 * Load DMA cycle times into the chip ready for a DMA transfer 123 * to occur. 124 */ 125 126static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev) 127{ 128 struct pci_dev *pdev = to_pci_dev(ap->host->dev); 129 int port = 0x60 + 8 * ap->port_no + 4 * adev->devno; 130 static u8 udma_timing[6][2] = { 131 { 0x60, 0x03 }, /* 33 Mhz Clock */ 132 { 0x40, 0x02 }, 133 { 0x20, 0x01 }, 134 { 0x40, 0x02 }, /* 66 Mhz Clock */ 135 { 0x20, 0x01 }, 136 { 0x20, 0x01 } 137 }; 138 static u8 mdma_timing[3][2] = { 139 { 0xe0, 0x0f }, 140 { 0x60, 0x04 }, 141 { 0x60, 0x03 }, 142 }; 143 u8 r_bp, r_cp; 144 145 pci_read_config_byte(pdev, port + 1, &r_bp); 146 pci_read_config_byte(pdev, port + 2, &r_cp); 147 148 r_bp &= ~0xE0; 149 r_cp &= ~0x0F; 150 151 if (adev->dma_mode >= XFER_UDMA_0) { 152 int speed = adev->dma_mode - XFER_UDMA_0; 153 r_bp |= udma_timing[speed][0]; 154 r_cp |= udma_timing[speed][1]; 155 156 } else { 157 int speed = adev->dma_mode - XFER_MW_DMA_0; 158 r_bp |= mdma_timing[speed][0]; 159 r_cp |= mdma_timing[speed][1]; 160 } 161 pci_write_config_byte(pdev, port + 1, r_bp); 162 pci_write_config_byte(pdev, port + 2, r_cp); 163 164} 165 166/** 167 * pdc2026x_bmdma_start - DMA engine begin 168 * @qc: ATA command 169 * 170 * In UDMA3 or higher we have to clock switch for the duration of the 171 * DMA transfer sequence. 172 * 173 * Note: The host lock held by the libata layer protects 174 * us from two channels both trying to set DMA bits at once 175 */ 176 177static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc) 178{ 179 struct ata_port *ap = qc->ap; 180 struct ata_device *adev = qc->dev; 181 struct ata_taskfile *tf = &qc->tf; 182 int sel66 = ap->port_no ? 0x08: 0x02; 183 184 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; 185 void __iomem *clock = master + 0x11; 186 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); 187 188 u32 len; 189 190 /* Check we keep host level locking here */ 191 if (adev->dma_mode > XFER_UDMA_2) 192 iowrite8(ioread8(clock) | sel66, clock); 193 else 194 iowrite8(ioread8(clock) & ~sel66, clock); 195 196 /* The DMA clocks may have been trashed by a reset. FIXME: make conditional 197 and move to qc_issue ? */ 198 pdc202xx_set_dmamode(ap, qc->dev); 199 200 /* Cases the state machine will not complete correctly without help */ 201 if ((tf->flags & ATA_TFLAG_LBA48) || tf->protocol == ATAPI_PROT_DMA) { 202 len = qc->nbytes / 2; 203 204 if (tf->flags & ATA_TFLAG_WRITE) 205 len |= 0x06000000; 206 else 207 len |= 0x05000000; 208 209 iowrite32(len, atapi_reg); 210 } 211 212 /* Activate DMA */ 213 ata_bmdma_start(qc); 214} 215 216/** 217 * pdc2026x_bmdma_end - DMA engine stop 218 * @qc: ATA command 219 * 220 * After a DMA completes we need to put the clock back to 33MHz for 221 * PIO timings. 222 * 223 * Note: The host lock held by the libata layer protects 224 * us from two channels both trying to set DMA bits at once 225 */ 226 227static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc) 228{ 229 struct ata_port *ap = qc->ap; 230 struct ata_device *adev = qc->dev; 231 struct ata_taskfile *tf = &qc->tf; 232 233 int sel66 = ap->port_no ? 0x08: 0x02; 234 /* The clock bits are in the same register for both channels */ 235 void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr; 236 void __iomem *clock = master + 0x11; 237 void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no); 238 239 /* Cases the state machine will not complete correctly */ 240 if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) { 241 iowrite32(0, atapi_reg); 242 iowrite8(ioread8(clock) & ~sel66, clock); 243 } 244 /* Flip back to 33Mhz for PIO */ 245 if (adev->dma_mode > XFER_UDMA_2) 246 iowrite8(ioread8(clock) & ~sel66, clock); 247 ata_bmdma_stop(qc); 248 pdc202xx_set_piomode(ap, adev); 249} 250 251/** 252 * pdc2026x_dev_config - device setup hook 253 * @adev: newly found device 254 * 255 * Perform chip specific early setup. We need to lock the transfer 256 * sizes to 8bit to avoid making the state engine on the 2026x cards 257 * barf. 258 */ 259 260static void pdc2026x_dev_config(struct ata_device *adev) 261{ 262 adev->max_sectors = 256; 263} 264 265static int pdc2026x_port_start(struct ata_port *ap) 266{ 267 void __iomem *bmdma = ap->ioaddr.bmdma_addr; 268 if (bmdma) { 269 /* Enable burst mode */ 270 u8 burst = ioread8(bmdma + 0x1f); 271 iowrite8(burst | 0x01, bmdma + 0x1f); 272 } 273 return ata_bmdma_port_start(ap); 274} 275 276/** 277 * pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command 278 * @qc: Metadata associated with taskfile to check 279 * 280 * Just say no - not supported on older Promise. 281 * 282 * LOCKING: 283 * None (inherited from caller). 284 * 285 * RETURNS: 0 when ATAPI DMA can be used 286 * 1 otherwise 287 */ 288 289static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc) 290{ 291 return 1; 292} 293 294static struct scsi_host_template pdc202xx_sht = { 295 ATA_BMDMA_SHT(DRV_NAME), 296}; 297 298static struct ata_port_operations pdc2024x_port_ops = { 299 .inherits = &ata_bmdma_port_ops, 300 301 .cable_detect = ata_cable_40wire, 302 .set_piomode = pdc202xx_set_piomode, 303 .set_dmamode = pdc202xx_set_dmamode, 304 305 .sff_exec_command = pdc202xx_exec_command, 306 .sff_irq_check = pdc202xx_irq_check, 307}; 308 309static struct ata_port_operations pdc2026x_port_ops = { 310 .inherits = &pdc2024x_port_ops, 311 312 .check_atapi_dma = pdc2026x_check_atapi_dma, 313 .bmdma_start = pdc2026x_bmdma_start, 314 .bmdma_stop = pdc2026x_bmdma_stop, 315 316 .cable_detect = pdc2026x_cable_detect, 317 .dev_config = pdc2026x_dev_config, 318 319 .port_start = pdc2026x_port_start, 320 321 .sff_exec_command = pdc202xx_exec_command, 322 .sff_irq_check = pdc202xx_irq_check, 323}; 324 325static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) 326{ 327 static const struct ata_port_info info[3] = { 328 { 329 .flags = ATA_FLAG_SLAVE_POSS, 330 .pio_mask = ATA_PIO4, 331 .mwdma_mask = ATA_MWDMA2, 332 .udma_mask = ATA_UDMA2, 333 .port_ops = &pdc2024x_port_ops 334 }, 335 { 336 .flags = ATA_FLAG_SLAVE_POSS, 337 .pio_mask = ATA_PIO4, 338 .mwdma_mask = ATA_MWDMA2, 339 .udma_mask = ATA_UDMA4, 340 .port_ops = &pdc2026x_port_ops 341 }, 342 { 343 .flags = ATA_FLAG_SLAVE_POSS, 344 .pio_mask = ATA_PIO4, 345 .mwdma_mask = ATA_MWDMA2, 346 .udma_mask = ATA_UDMA5, 347 .port_ops = &pdc2026x_port_ops 348 } 349 350 }; 351 const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL }; 352 353 if (dev->device == PCI_DEVICE_ID_PROMISE_20265) { 354 struct pci_dev *bridge = dev->bus->self; 355 /* Don't grab anything behind a Promise I2O RAID */ 356 if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) { 357 if (bridge->device == PCI_DEVICE_ID_INTEL_I960) 358 return -ENODEV; 359 if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM) 360 return -ENODEV; 361 } 362 } 363 return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0); 364} 365 366static const struct pci_device_id pdc202xx[] = { 367 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 }, 368 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 }, 369 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 }, 370 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 }, 371 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 }, 372 373 { }, 374}; 375 376static struct pci_driver pdc202xx_pci_driver = { 377 .name = DRV_NAME, 378 .id_table = pdc202xx, 379 .probe = pdc202xx_init_one, 380 .remove = ata_pci_remove_one, 381#ifdef CONFIG_PM 382 .suspend = ata_pci_device_suspend, 383 .resume = ata_pci_device_resume, 384#endif 385}; 386 387static int __init pdc202xx_init(void) 388{ 389 return pci_register_driver(&pdc202xx_pci_driver); 390} 391 392static void __exit pdc202xx_exit(void) 393{ 394 pci_unregister_driver(&pdc202xx_pci_driver); 395} 396 397MODULE_AUTHOR("Alan Cox"); 398MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267"); 399MODULE_LICENSE("GPL"); 400MODULE_DEVICE_TABLE(pci, pdc202xx); 401MODULE_VERSION(DRV_VERSION); 402 403module_init(pdc202xx_init); 404module_exit(pdc202xx_exit); 405