1/* 2 * drivers/ata/sata_fsl.c 3 * 4 * Freescale 3.0Gbps SATA device driver 5 * 6 * Author: Ashish Kalra <ashish.kalra@freescale.com> 7 * Li Yang <leoli@freescale.com> 8 * 9 * Copyright (c) 2006-2007, 2011 Freescale Semiconductor, Inc. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 */ 17 18#include <linux/kernel.h> 19#include <linux/module.h> 20#include <linux/platform_device.h> 21#include <linux/slab.h> 22 23#include <scsi/scsi_host.h> 24#include <scsi/scsi_cmnd.h> 25#include <linux/libata.h> 26#include <asm/io.h> 27#include <linux/of_platform.h> 28 29/* Controller information */ 30enum { 31 SATA_FSL_QUEUE_DEPTH = 16, 32 SATA_FSL_MAX_PRD = 63, 33 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, 34 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ 35 36 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | 37 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN), 38 39 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, 40 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ 41 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), 42 43 /* 44 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and 45 * chained indirect PRDEs up to a max count of 63. 46 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will 47 * be setup as an indirect descriptor, pointing to it's next 48 * (contiguous) PRDE. Though chained indirect PRDE arrays are 49 * supported,it will be more efficient to use a direct PRDT and 50 * a single chain/link to indirect PRDE array/PRDT. 51 */ 52 53 SATA_FSL_CMD_DESC_CFIS_SZ = 32, 54 SATA_FSL_CMD_DESC_SFIS_SZ = 32, 55 SATA_FSL_CMD_DESC_ACMD_SZ = 16, 56 SATA_FSL_CMD_DESC_RSRVD = 16, 57 58 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + 59 SATA_FSL_CMD_DESC_SFIS_SZ + 60 SATA_FSL_CMD_DESC_ACMD_SZ + 61 SATA_FSL_CMD_DESC_RSRVD + 62 SATA_FSL_MAX_PRD * 16), 63 64 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = 65 (SATA_FSL_CMD_DESC_CFIS_SZ + 66 SATA_FSL_CMD_DESC_SFIS_SZ + 67 SATA_FSL_CMD_DESC_ACMD_SZ + 68 SATA_FSL_CMD_DESC_RSRVD), 69 70 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), 71 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + 72 SATA_FSL_CMD_DESC_AR_SZ), 73 74 /* 75 * MPC8315 has two SATA controllers, SATA1 & SATA2 76 * (one port per controller) 77 * MPC837x has 2/4 controllers, one port per controller 78 */ 79 80 SATA_FSL_MAX_PORTS = 1, 81 82 SATA_FSL_IRQ_FLAG = IRQF_SHARED, 83}; 84 85/* 86* Host Controller command register set - per port 87*/ 88enum { 89 CQ = 0, 90 CA = 8, 91 CC = 0x10, 92 CE = 0x18, 93 DE = 0x20, 94 CHBA = 0x24, 95 HSTATUS = 0x28, 96 HCONTROL = 0x2C, 97 CQPMP = 0x30, 98 SIGNATURE = 0x34, 99 ICC = 0x38, 100 101 /* 102 * Host Status Register (HStatus) bitdefs 103 */ 104 ONLINE = (1 << 31), 105 GOING_OFFLINE = (1 << 30), 106 BIST_ERR = (1 << 29), 107 108 FATAL_ERR_HC_MASTER_ERR = (1 << 18), 109 FATAL_ERR_PARITY_ERR_TX = (1 << 17), 110 FATAL_ERR_PARITY_ERR_RX = (1 << 16), 111 FATAL_ERR_DATA_UNDERRUN = (1 << 13), 112 FATAL_ERR_DATA_OVERRUN = (1 << 12), 113 FATAL_ERR_CRC_ERR_TX = (1 << 11), 114 FATAL_ERR_CRC_ERR_RX = (1 << 10), 115 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), 116 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), 117 118 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | 119 FATAL_ERR_PARITY_ERR_TX | 120 FATAL_ERR_PARITY_ERR_RX | 121 FATAL_ERR_DATA_UNDERRUN | 122 FATAL_ERR_DATA_OVERRUN | 123 FATAL_ERR_CRC_ERR_TX | 124 FATAL_ERR_CRC_ERR_RX | 125 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, 126 127 INT_ON_FATAL_ERR = (1 << 5), 128 INT_ON_PHYRDY_CHG = (1 << 4), 129 130 INT_ON_SIGNATURE_UPDATE = (1 << 3), 131 INT_ON_SNOTIFY_UPDATE = (1 << 2), 132 INT_ON_SINGL_DEVICE_ERR = (1 << 1), 133 INT_ON_CMD_COMPLETE = 1, 134 135 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | 136 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, 137 138 /* 139 * Host Control Register (HControl) bitdefs 140 */ 141 HCONTROL_ONLINE_PHY_RST = (1 << 31), 142 HCONTROL_FORCE_OFFLINE = (1 << 30), 143 HCONTROL_LEGACY = (1 << 28), 144 HCONTROL_PARITY_PROT_MOD = (1 << 14), 145 HCONTROL_DPATH_PARITY = (1 << 12), 146 HCONTROL_SNOOP_ENABLE = (1 << 10), 147 HCONTROL_PMP_ATTACHED = (1 << 9), 148 HCONTROL_COPYOUT_STATFIS = (1 << 8), 149 IE_ON_FATAL_ERR = (1 << 5), 150 IE_ON_PHYRDY_CHG = (1 << 4), 151 IE_ON_SIGNATURE_UPDATE = (1 << 3), 152 IE_ON_SNOTIFY_UPDATE = (1 << 2), 153 IE_ON_SINGL_DEVICE_ERR = (1 << 1), 154 IE_ON_CMD_COMPLETE = 1, 155 156 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | 157 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | 158 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, 159 160 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), 161 DATA_SNOOP_ENABLE_V1 = (1 << 22), 162 DATA_SNOOP_ENABLE_V2 = (1 << 28), 163}; 164 165/* 166 * SATA Superset Registers 167 */ 168enum { 169 SSTATUS = 0, 170 SERROR = 4, 171 SCONTROL = 8, 172 SNOTIFY = 0xC, 173}; 174 175/* 176 * Control Status Register Set 177 */ 178enum { 179 TRANSCFG = 0, 180 TRANSSTATUS = 4, 181 LINKCFG = 8, 182 LINKCFG1 = 0xC, 183 LINKCFG2 = 0x10, 184 LINKSTATUS = 0x14, 185 LINKSTATUS1 = 0x18, 186 PHYCTRLCFG = 0x1C, 187 COMMANDSTAT = 0x20, 188}; 189 190/* TRANSCFG (transport-layer) configuration control */ 191enum { 192 TRANSCFG_RX_WATER_MARK = (1 << 4), 193}; 194 195/* PHY (link-layer) configuration control */ 196enum { 197 PHY_BIST_ENABLE = 0x01, 198}; 199 200/* 201 * Command Header Table entry, i.e, command slot 202 * 4 Dwords per command slot, command header size == 64 Dwords. 203 */ 204struct cmdhdr_tbl_entry { 205 u32 cda; 206 u32 prde_fis_len; 207 u32 ttl; 208 u32 desc_info; 209}; 210 211/* 212 * Description information bitdefs 213 */ 214enum { 215 CMD_DESC_RES = (1 << 11), 216 VENDOR_SPECIFIC_BIST = (1 << 10), 217 CMD_DESC_SNOOP_ENABLE = (1 << 9), 218 FPDMA_QUEUED_CMD = (1 << 8), 219 SRST_CMD = (1 << 7), 220 BIST = (1 << 6), 221 ATAPI_CMD = (1 << 5), 222}; 223 224/* 225 * Command Descriptor 226 */ 227struct command_desc { 228 u8 cfis[8 * 4]; 229 u8 sfis[8 * 4]; 230 u8 acmd[4 * 4]; 231 u8 fill[4 * 4]; 232 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; 233 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; 234}; 235 236/* 237 * Physical region table descriptor(PRD) 238 */ 239 240struct prde { 241 u32 dba; 242 u8 fill[2 * 4]; 243 u32 ddc_and_ext; 244}; 245 246/* 247 * ata_port private data 248 * This is our per-port instance data. 249 */ 250struct sata_fsl_port_priv { 251 struct cmdhdr_tbl_entry *cmdslot; 252 dma_addr_t cmdslot_paddr; 253 struct command_desc *cmdentry; 254 dma_addr_t cmdentry_paddr; 255}; 256 257/* 258 * ata_port->host_set private data 259 */ 260struct sata_fsl_host_priv { 261 void __iomem *hcr_base; 262 void __iomem *ssr_base; 263 void __iomem *csr_base; 264 int irq; 265 int data_snoop; 266}; 267 268static inline unsigned int sata_fsl_tag(unsigned int tag, 269 void __iomem *hcr_base) 270{ 271 /* We let libATA core do actual (queue) tag allocation */ 272 273 /* all non NCQ/queued commands should have tag#0 */ 274 if (ata_tag_internal(tag)) { 275 DPRINTK("mapping internal cmds to tag#0\n"); 276 return 0; 277 } 278 279 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { 280 DPRINTK("tag %d invalid : out of range\n", tag); 281 return 0; 282 } 283 284 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { 285 DPRINTK("tag %d invalid : in use!!\n", tag); 286 return 0; 287 } 288 289 return tag; 290} 291 292static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, 293 unsigned int tag, u32 desc_info, 294 u32 data_xfer_len, u8 num_prde, 295 u8 fis_len) 296{ 297 dma_addr_t cmd_descriptor_address; 298 299 cmd_descriptor_address = pp->cmdentry_paddr + 300 tag * SATA_FSL_CMD_DESC_SIZE; 301 302 /* NOTE: both data_xfer_len & fis_len are Dword counts */ 303 304 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); 305 pp->cmdslot[tag].prde_fis_len = 306 cpu_to_le32((num_prde << 16) | (fis_len << 2)); 307 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); 308 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); 309 310 VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", 311 pp->cmdslot[tag].cda, 312 pp->cmdslot[tag].prde_fis_len, 313 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); 314 315} 316 317static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, 318 u32 *ttl, dma_addr_t cmd_desc_paddr, 319 int data_snoop) 320{ 321 struct scatterlist *sg; 322 unsigned int num_prde = 0; 323 u32 ttl_dwords = 0; 324 325 /* 326 * NOTE : direct & indirect prdt's are contiguously allocated 327 */ 328 struct prde *prd = (struct prde *)&((struct command_desc *) 329 cmd_desc)->prdt; 330 331 struct prde *prd_ptr_to_indirect_ext = NULL; 332 unsigned indirect_ext_segment_sz = 0; 333 dma_addr_t indirect_ext_segment_paddr; 334 unsigned int si; 335 336 VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); 337 338 indirect_ext_segment_paddr = cmd_desc_paddr + 339 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; 340 341 for_each_sg(qc->sg, sg, qc->n_elem, si) { 342 dma_addr_t sg_addr = sg_dma_address(sg); 343 u32 sg_len = sg_dma_len(sg); 344 345 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", 346 (unsigned long long)sg_addr, sg_len); 347 348 /* warn if each s/g element is not dword aligned */ 349 if (sg_addr & 0x03) 350 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n", 351 (unsigned long long)sg_addr); 352 if (sg_len & 0x03) 353 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n", 354 sg_len); 355 356 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && 357 sg_next(sg) != NULL) { 358 VPRINTK("setting indirect prde\n"); 359 prd_ptr_to_indirect_ext = prd; 360 prd->dba = cpu_to_le32(indirect_ext_segment_paddr); 361 indirect_ext_segment_sz = 0; 362 ++prd; 363 ++num_prde; 364 } 365 366 ttl_dwords += sg_len; 367 prd->dba = cpu_to_le32(sg_addr); 368 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); 369 370 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", 371 ttl_dwords, prd->dba, prd->ddc_and_ext); 372 373 ++num_prde; 374 ++prd; 375 if (prd_ptr_to_indirect_ext) 376 indirect_ext_segment_sz += sg_len; 377 } 378 379 if (prd_ptr_to_indirect_ext) { 380 /* set indirect extension flag along with indirect ext. size */ 381 prd_ptr_to_indirect_ext->ddc_and_ext = 382 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | 383 data_snoop | 384 (indirect_ext_segment_sz & ~0x03))); 385 } 386 387 *ttl = ttl_dwords; 388 return num_prde; 389} 390 391static void sata_fsl_qc_prep(struct ata_queued_cmd *qc) 392{ 393 struct ata_port *ap = qc->ap; 394 struct sata_fsl_port_priv *pp = ap->private_data; 395 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 396 void __iomem *hcr_base = host_priv->hcr_base; 397 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 398 struct command_desc *cd; 399 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; 400 u32 num_prde = 0; 401 u32 ttl_dwords = 0; 402 dma_addr_t cd_paddr; 403 404 cd = (struct command_desc *)pp->cmdentry + tag; 405 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; 406 407 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); 408 409 VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", 410 cd->cfis[0], cd->cfis[1], cd->cfis[2]); 411 412 if (qc->tf.protocol == ATA_PROT_NCQ) { 413 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", 414 cd->cfis[3], cd->cfis[11]); 415 } 416 417 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ 418 if (ata_is_atapi(qc->tf.protocol)) { 419 desc_info |= ATAPI_CMD; 420 memset((void *)&cd->acmd, 0, 32); 421 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len); 422 } 423 424 if (qc->flags & ATA_QCFLAG_DMAMAP) 425 num_prde = sata_fsl_fill_sg(qc, (void *)cd, 426 &ttl_dwords, cd_paddr, 427 host_priv->data_snoop); 428 429 if (qc->tf.protocol == ATA_PROT_NCQ) 430 desc_info |= FPDMA_QUEUED_CMD; 431 432 sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, 433 num_prde, 5); 434 435 VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", 436 desc_info, ttl_dwords, num_prde); 437} 438 439static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) 440{ 441 struct ata_port *ap = qc->ap; 442 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 443 void __iomem *hcr_base = host_priv->hcr_base; 444 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 445 446 VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", 447 ioread32(CQ + hcr_base), 448 ioread32(CA + hcr_base), 449 ioread32(CE + hcr_base), ioread32(CC + hcr_base)); 450 451 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); 452 453 /* Simply queue command to the controller/device */ 454 iowrite32(1 << tag, CQ + hcr_base); 455 456 VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", 457 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); 458 459 VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", 460 ioread32(CE + hcr_base), 461 ioread32(DE + hcr_base), 462 ioread32(CC + hcr_base), 463 ioread32(COMMANDSTAT + host_priv->csr_base)); 464 465 return 0; 466} 467 468static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) 469{ 470 struct sata_fsl_port_priv *pp = qc->ap->private_data; 471 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; 472 void __iomem *hcr_base = host_priv->hcr_base; 473 unsigned int tag = sata_fsl_tag(qc->tag, hcr_base); 474 struct command_desc *cd; 475 476 cd = pp->cmdentry + tag; 477 478 ata_tf_from_fis(cd->sfis, &qc->result_tf); 479 return true; 480} 481 482static int sata_fsl_scr_write(struct ata_link *link, 483 unsigned int sc_reg_in, u32 val) 484{ 485 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 486 void __iomem *ssr_base = host_priv->ssr_base; 487 unsigned int sc_reg; 488 489 switch (sc_reg_in) { 490 case SCR_STATUS: 491 case SCR_ERROR: 492 case SCR_CONTROL: 493 case SCR_ACTIVE: 494 sc_reg = sc_reg_in; 495 break; 496 default: 497 return -EINVAL; 498 } 499 500 VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); 501 502 iowrite32(val, ssr_base + (sc_reg * 4)); 503 return 0; 504} 505 506static int sata_fsl_scr_read(struct ata_link *link, 507 unsigned int sc_reg_in, u32 *val) 508{ 509 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; 510 void __iomem *ssr_base = host_priv->ssr_base; 511 unsigned int sc_reg; 512 513 switch (sc_reg_in) { 514 case SCR_STATUS: 515 case SCR_ERROR: 516 case SCR_CONTROL: 517 case SCR_ACTIVE: 518 sc_reg = sc_reg_in; 519 break; 520 default: 521 return -EINVAL; 522 } 523 524 VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); 525 526 *val = ioread32(ssr_base + (sc_reg * 4)); 527 return 0; 528} 529 530static void sata_fsl_freeze(struct ata_port *ap) 531{ 532 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 533 void __iomem *hcr_base = host_priv->hcr_base; 534 u32 temp; 535 536 VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", 537 ioread32(CQ + hcr_base), 538 ioread32(CA + hcr_base), 539 ioread32(CE + hcr_base), ioread32(DE + hcr_base)); 540 VPRINTK("CmdStat = 0x%x\n", 541 ioread32(host_priv->csr_base + COMMANDSTAT)); 542 543 /* disable interrupts on the controller/port */ 544 temp = ioread32(hcr_base + HCONTROL); 545 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 546 547 VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", 548 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 549} 550 551static void sata_fsl_thaw(struct ata_port *ap) 552{ 553 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 554 void __iomem *hcr_base = host_priv->hcr_base; 555 u32 temp; 556 557 /* ack. any pending IRQs for this controller/port */ 558 temp = ioread32(hcr_base + HSTATUS); 559 560 VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); 561 562 if (temp & 0x3F) 563 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 564 565 /* enable interrupts on the controller/port */ 566 temp = ioread32(hcr_base + HCONTROL); 567 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 568 569 VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", 570 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); 571} 572 573static void sata_fsl_pmp_attach(struct ata_port *ap) 574{ 575 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 576 void __iomem *hcr_base = host_priv->hcr_base; 577 u32 temp; 578 579 temp = ioread32(hcr_base + HCONTROL); 580 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); 581} 582 583static void sata_fsl_pmp_detach(struct ata_port *ap) 584{ 585 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 586 void __iomem *hcr_base = host_priv->hcr_base; 587 u32 temp; 588 589 temp = ioread32(hcr_base + HCONTROL); 590 temp &= ~HCONTROL_PMP_ATTACHED; 591 iowrite32(temp, hcr_base + HCONTROL); 592 593 /* enable interrupts on the controller/port */ 594 temp = ioread32(hcr_base + HCONTROL); 595 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); 596 597} 598 599static int sata_fsl_port_start(struct ata_port *ap) 600{ 601 struct device *dev = ap->host->dev; 602 struct sata_fsl_port_priv *pp; 603 void *mem; 604 dma_addr_t mem_dma; 605 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 606 void __iomem *hcr_base = host_priv->hcr_base; 607 u32 temp; 608 609 pp = kzalloc(sizeof(*pp), GFP_KERNEL); 610 if (!pp) 611 return -ENOMEM; 612 613 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, 614 GFP_KERNEL); 615 if (!mem) { 616 kfree(pp); 617 return -ENOMEM; 618 } 619 memset(mem, 0, SATA_FSL_PORT_PRIV_DMA_SZ); 620 621 pp->cmdslot = mem; 622 pp->cmdslot_paddr = mem_dma; 623 624 mem += SATA_FSL_CMD_SLOT_SIZE; 625 mem_dma += SATA_FSL_CMD_SLOT_SIZE; 626 627 pp->cmdentry = mem; 628 pp->cmdentry_paddr = mem_dma; 629 630 ap->private_data = pp; 631 632 VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", 633 pp->cmdslot_paddr, pp->cmdentry_paddr); 634 635 /* Now, update the CHBA register in host controller cmd register set */ 636 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 637 638 /* 639 * Now, we can bring the controller on-line & also initiate 640 * the COMINIT sequence, we simply return here and the boot-probing 641 * & device discovery process is re-initiated by libATA using a 642 * Softreset EH (dummy) session. Hence, boot probing and device 643 * discovey will be part of sata_fsl_softreset() callback. 644 */ 645 646 temp = ioread32(hcr_base + HCONTROL); 647 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); 648 649 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 650 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 651 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); 652 653#ifdef CONFIG_MPC8315_DS 654 /* 655 * Workaround for 8315DS board 3gbps link-up issue, 656 * currently limit SATA port to GEN1 speed 657 */ 658 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 659 temp &= ~(0xF << 4); 660 temp |= (0x1 << 4); 661 sata_fsl_scr_write(&ap->link, SCR_CONTROL, temp); 662 663 sata_fsl_scr_read(&ap->link, SCR_CONTROL, &temp); 664 dev_warn(dev, "scr_control, speed limited to %x\n", temp); 665#endif 666 667 return 0; 668} 669 670static void sata_fsl_port_stop(struct ata_port *ap) 671{ 672 struct device *dev = ap->host->dev; 673 struct sata_fsl_port_priv *pp = ap->private_data; 674 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 675 void __iomem *hcr_base = host_priv->hcr_base; 676 u32 temp; 677 678 /* 679 * Force host controller to go off-line, aborting current operations 680 */ 681 temp = ioread32(hcr_base + HCONTROL); 682 temp &= ~HCONTROL_ONLINE_PHY_RST; 683 temp |= HCONTROL_FORCE_OFFLINE; 684 iowrite32(temp, hcr_base + HCONTROL); 685 686 /* Poll for controller to go offline - should happen immediately */ 687 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); 688 689 ap->private_data = NULL; 690 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, 691 pp->cmdslot, pp->cmdslot_paddr); 692 693 kfree(pp); 694} 695 696static unsigned int sata_fsl_dev_classify(struct ata_port *ap) 697{ 698 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 699 void __iomem *hcr_base = host_priv->hcr_base; 700 struct ata_taskfile tf; 701 u32 temp; 702 703 temp = ioread32(hcr_base + SIGNATURE); 704 705 VPRINTK("raw sig = 0x%x\n", temp); 706 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 707 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 708 709 tf.lbah = (temp >> 24) & 0xff; 710 tf.lbam = (temp >> 16) & 0xff; 711 tf.lbal = (temp >> 8) & 0xff; 712 tf.nsect = temp & 0xff; 713 714 return ata_dev_classify(&tf); 715} 716 717static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, 718 unsigned long deadline) 719{ 720 struct ata_port *ap = link->ap; 721 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 722 void __iomem *hcr_base = host_priv->hcr_base; 723 u32 temp; 724 int i = 0; 725 unsigned long start_jiffies; 726 727 DPRINTK("in xx_hardreset\n"); 728 729try_offline_again: 730 /* 731 * Force host controller to go off-line, aborting current operations 732 */ 733 temp = ioread32(hcr_base + HCONTROL); 734 temp &= ~HCONTROL_ONLINE_PHY_RST; 735 iowrite32(temp, hcr_base + HCONTROL); 736 737 /* Poll for controller to go offline */ 738 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 739 1, 500); 740 741 if (temp & ONLINE) { 742 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i); 743 744 /* 745 * Try to offline controller atleast twice 746 */ 747 i++; 748 if (i == 2) 749 goto err; 750 else 751 goto try_offline_again; 752 } 753 754 DPRINTK("hardreset, controller off-lined\n"); 755 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 756 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 757 758 /* 759 * PHY reset should remain asserted for atleast 1ms 760 */ 761 ata_msleep(ap, 1); 762 763 /* 764 * Now, bring the host controller online again, this can take time 765 * as PHY reset and communication establishment, 1st D2H FIS and 766 * device signature update is done, on safe side assume 500ms 767 * NOTE : Host online status may be indicated immediately!! 768 */ 769 770 temp = ioread32(hcr_base + HCONTROL); 771 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); 772 temp |= HCONTROL_PMP_ATTACHED; 773 iowrite32(temp, hcr_base + HCONTROL); 774 775 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); 776 777 if (!(temp & ONLINE)) { 778 ata_port_err(ap, "Hardreset failed, not on-lined\n"); 779 goto err; 780 } 781 782 DPRINTK("hardreset, controller off-lined & on-lined\n"); 783 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 784 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 785 786 /* 787 * First, wait for the PHYRDY change to occur before waiting for 788 * the signature, and also verify if SStatus indicates device 789 * presence 790 */ 791 792 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); 793 if ((!(temp & 0x10)) || ata_link_offline(link)) { 794 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n", 795 ioread32(hcr_base + HSTATUS)); 796 *class = ATA_DEV_NONE; 797 return 0; 798 } 799 800 /* 801 * Wait for the first D2H from device,i.e,signature update notification 802 */ 803 start_jiffies = jiffies; 804 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, 805 500, jiffies_to_msecs(deadline - start_jiffies)); 806 807 if ((temp & 0xFF) != 0x18) { 808 ata_port_warn(ap, "No Signature Update\n"); 809 *class = ATA_DEV_NONE; 810 goto do_followup_srst; 811 } else { 812 ata_port_info(ap, "Signature Update detected @ %d msecs\n", 813 jiffies_to_msecs(jiffies - start_jiffies)); 814 *class = sata_fsl_dev_classify(ap); 815 return 0; 816 } 817 818do_followup_srst: 819 /* 820 * request libATA to perform follow-up softreset 821 */ 822 return -EAGAIN; 823 824err: 825 return -EIO; 826} 827 828static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, 829 unsigned long deadline) 830{ 831 struct ata_port *ap = link->ap; 832 struct sata_fsl_port_priv *pp = ap->private_data; 833 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 834 void __iomem *hcr_base = host_priv->hcr_base; 835 int pmp = sata_srst_pmp(link); 836 u32 temp; 837 struct ata_taskfile tf; 838 u8 *cfis; 839 u32 Serror; 840 841 DPRINTK("in xx_softreset\n"); 842 843 if (ata_link_offline(link)) { 844 DPRINTK("PHY reports no device\n"); 845 *class = ATA_DEV_NONE; 846 return 0; 847 } 848 849 /* 850 * Send a device reset (SRST) explicitly on command slot #0 851 * Check : will the command queue (reg) be cleared during offlining ?? 852 * Also we will be online only if Phy commn. has been established 853 * and device presence has been detected, therefore if we have 854 * reached here, we can send a command to the target device 855 */ 856 857 DPRINTK("Sending SRST/device reset\n"); 858 859 ata_tf_init(link->device, &tf); 860 cfis = (u8 *) &pp->cmdentry->cfis; 861 862 /* device reset/SRST is a control register update FIS, uses tag0 */ 863 sata_fsl_setup_cmd_hdr_entry(pp, 0, 864 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); 865 866 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ 867 ata_tf_to_fis(&tf, pmp, 0, cfis); 868 869 DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", 870 cfis[0], cfis[1], cfis[2], cfis[3]); 871 872 /* 873 * Queue SRST command to the controller/device, ensure that no 874 * other commands are active on the controller/device 875 */ 876 877 DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", 878 ioread32(CQ + hcr_base), 879 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 880 881 iowrite32(0xFFFF, CC + hcr_base); 882 if (pmp != SATA_PMP_CTRL_PORT) 883 iowrite32(pmp, CQPMP + hcr_base); 884 iowrite32(1, CQ + hcr_base); 885 886 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); 887 if (temp & 0x1) { 888 ata_port_warn(ap, "ATA_SRST issue failed\n"); 889 890 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", 891 ioread32(CQ + hcr_base), 892 ioread32(CA + hcr_base), ioread32(CC + hcr_base)); 893 894 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); 895 896 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 897 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 898 DPRINTK("Serror = 0x%x\n", Serror); 899 goto err; 900 } 901 902 ata_msleep(ap, 1); 903 904 /* 905 * SATA device enters reset state after receiving a Control register 906 * FIS with SRST bit asserted and it awaits another H2D Control reg. 907 * FIS with SRST bit cleared, then the device does internal diags & 908 * initialization, followed by indicating it's initialization status 909 * using ATA signature D2H register FIS to the host controller. 910 */ 911 912 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 913 0, 0, 5); 914 915 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ 916 ata_tf_to_fis(&tf, pmp, 0, cfis); 917 918 if (pmp != SATA_PMP_CTRL_PORT) 919 iowrite32(pmp, CQPMP + hcr_base); 920 iowrite32(1, CQ + hcr_base); 921 ata_msleep(ap, 150); /* ?? */ 922 923 /* 924 * The above command would have signalled an interrupt on command 925 * complete, which needs special handling, by clearing the Nth 926 * command bit of the CCreg 927 */ 928 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ 929 930 DPRINTK("SATA FSL : Now checking device signature\n"); 931 932 *class = ATA_DEV_NONE; 933 934 /* Verify if SStatus indicates device presence */ 935 if (ata_link_online(link)) { 936 /* 937 * if we are here, device presence has been detected, 938 * 1st D2H FIS would have been received, but sfis in 939 * command desc. is not updated, but signature register 940 * would have been updated 941 */ 942 943 *class = sata_fsl_dev_classify(ap); 944 945 DPRINTK("class = %d\n", *class); 946 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); 947 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); 948 } 949 950 return 0; 951 952err: 953 return -EIO; 954} 955 956static void sata_fsl_error_handler(struct ata_port *ap) 957{ 958 959 DPRINTK("in xx_error_handler\n"); 960 sata_pmp_error_handler(ap); 961 962} 963 964static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) 965{ 966 if (qc->flags & ATA_QCFLAG_FAILED) 967 qc->err_mask |= AC_ERR_OTHER; 968 969 if (qc->err_mask) { 970 /* make DMA engine forget about the failed command */ 971 972 } 973} 974 975static void sata_fsl_error_intr(struct ata_port *ap) 976{ 977 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 978 void __iomem *hcr_base = host_priv->hcr_base; 979 u32 hstatus, dereg=0, cereg = 0, SError = 0; 980 unsigned int err_mask = 0, action = 0; 981 int freeze = 0, abort=0; 982 struct ata_link *link = NULL; 983 struct ata_queued_cmd *qc = NULL; 984 struct ata_eh_info *ehi; 985 986 hstatus = ioread32(hcr_base + HSTATUS); 987 cereg = ioread32(hcr_base + CE); 988 989 /* first, analyze and record host port events */ 990 link = &ap->link; 991 ehi = &link->eh_info; 992 ata_ehi_clear_desc(ehi); 993 994 /* 995 * Handle & Clear SError 996 */ 997 998 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 999 if (unlikely(SError & 0xFFFF0000)) 1000 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); 1001 1002 DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", 1003 hstatus, cereg, ioread32(hcr_base + DE), SError); 1004 1005 /* handle fatal errors */ 1006 if (hstatus & FATAL_ERROR_DECODE) { 1007 ehi->err_mask |= AC_ERR_ATA_BUS; 1008 ehi->action |= ATA_EH_SOFTRESET; 1009 1010 freeze = 1; 1011 } 1012 1013 /* Handle SDB FIS receive & notify update */ 1014 if (hstatus & INT_ON_SNOTIFY_UPDATE) 1015 sata_async_notification(ap); 1016 1017 /* Handle PHYRDY change notification */ 1018 if (hstatus & INT_ON_PHYRDY_CHG) { 1019 DPRINTK("SATA FSL: PHYRDY change indication\n"); 1020 1021 /* Setup a soft-reset EH action */ 1022 ata_ehi_hotplugged(ehi); 1023 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); 1024 freeze = 1; 1025 } 1026 1027 /* handle single device errors */ 1028 if (cereg) { 1029 /* 1030 * clear the command error, also clears queue to the device 1031 * in error, and we can (re)issue commands to this device. 1032 * When a device is in error all commands queued into the 1033 * host controller and at the device are considered aborted 1034 * and the queue for that device is stopped. Now, after 1035 * clearing the device error, we can issue commands to the 1036 * device to interrogate it to find the source of the error. 1037 */ 1038 abort = 1; 1039 1040 DPRINTK("single device error, CE=0x%x, DE=0x%x\n", 1041 ioread32(hcr_base + CE), ioread32(hcr_base + DE)); 1042 1043 /* find out the offending link and qc */ 1044 if (ap->nr_pmp_links) { 1045 unsigned int dev_num; 1046 1047 dereg = ioread32(hcr_base + DE); 1048 iowrite32(dereg, hcr_base + DE); 1049 iowrite32(cereg, hcr_base + CE); 1050 1051 dev_num = ffs(dereg) - 1; 1052 if (dev_num < ap->nr_pmp_links && dereg != 0) { 1053 link = &ap->pmp_link[dev_num]; 1054 ehi = &link->eh_info; 1055 qc = ata_qc_from_tag(ap, link->active_tag); 1056 /* 1057 * We should consider this as non fatal error, 1058 * and TF must be updated as done below. 1059 */ 1060 1061 err_mask |= AC_ERR_DEV; 1062 1063 } else { 1064 err_mask |= AC_ERR_HSM; 1065 action |= ATA_EH_HARDRESET; 1066 freeze = 1; 1067 } 1068 } else { 1069 dereg = ioread32(hcr_base + DE); 1070 iowrite32(dereg, hcr_base + DE); 1071 iowrite32(cereg, hcr_base + CE); 1072 1073 qc = ata_qc_from_tag(ap, link->active_tag); 1074 /* 1075 * We should consider this as non fatal error, 1076 * and TF must be updated as done below. 1077 */ 1078 err_mask |= AC_ERR_DEV; 1079 } 1080 } 1081 1082 /* record error info */ 1083 if (qc) 1084 qc->err_mask |= err_mask; 1085 else 1086 ehi->err_mask |= err_mask; 1087 1088 ehi->action |= action; 1089 1090 /* freeze or abort */ 1091 if (freeze) 1092 ata_port_freeze(ap); 1093 else if (abort) { 1094 if (qc) 1095 ata_link_abort(qc->dev->link); 1096 else 1097 ata_port_abort(ap); 1098 } 1099} 1100 1101static void sata_fsl_host_intr(struct ata_port *ap) 1102{ 1103 struct sata_fsl_host_priv *host_priv = ap->host->private_data; 1104 void __iomem *hcr_base = host_priv->hcr_base; 1105 u32 hstatus, done_mask = 0; 1106 struct ata_queued_cmd *qc; 1107 u32 SError; 1108 1109 hstatus = ioread32(hcr_base + HSTATUS); 1110 1111 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); 1112 1113 if (unlikely(SError & 0xFFFF0000)) { 1114 DPRINTK("serror @host_intr : 0x%x\n", SError); 1115 sata_fsl_error_intr(ap); 1116 } 1117 1118 if (unlikely(hstatus & INT_ON_ERROR)) { 1119 DPRINTK("error interrupt!!\n"); 1120 sata_fsl_error_intr(ap); 1121 return; 1122 } 1123 1124 /* Read command completed register */ 1125 done_mask = ioread32(hcr_base + CC); 1126 1127 VPRINTK("Status of all queues :\n"); 1128 VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n", 1129 done_mask, 1130 ioread32(hcr_base + CA), 1131 ioread32(hcr_base + CE), 1132 ioread32(hcr_base + CQ), 1133 ap->qc_active); 1134 1135 if (done_mask & ap->qc_active) { 1136 int i; 1137 /* clear CC bit, this will also complete the interrupt */ 1138 iowrite32(done_mask, hcr_base + CC); 1139 1140 DPRINTK("Status of all queues :\n"); 1141 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", 1142 done_mask, ioread32(hcr_base + CA), 1143 ioread32(hcr_base + CE)); 1144 1145 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { 1146 if (done_mask & (1 << i)) 1147 DPRINTK 1148 ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", 1149 i, ioread32(hcr_base + CC), 1150 ioread32(hcr_base + CA)); 1151 } 1152 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask); 1153 return; 1154 1155 } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) { 1156 iowrite32(1, hcr_base + CC); 1157 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); 1158 1159 DPRINTK("completing non-ncq cmd, CC=0x%x\n", 1160 ioread32(hcr_base + CC)); 1161 1162 if (qc) { 1163 ata_qc_complete(qc); 1164 } 1165 } else { 1166 /* Spurious Interrupt!! */ 1167 DPRINTK("spurious interrupt!!, CC = 0x%x\n", 1168 ioread32(hcr_base + CC)); 1169 iowrite32(done_mask, hcr_base + CC); 1170 return; 1171 } 1172} 1173 1174static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) 1175{ 1176 struct ata_host *host = dev_instance; 1177 struct sata_fsl_host_priv *host_priv = host->private_data; 1178 void __iomem *hcr_base = host_priv->hcr_base; 1179 u32 interrupt_enables; 1180 unsigned handled = 0; 1181 struct ata_port *ap; 1182 1183 /* ack. any pending IRQs for this controller/port */ 1184 interrupt_enables = ioread32(hcr_base + HSTATUS); 1185 interrupt_enables &= 0x3F; 1186 1187 DPRINTK("interrupt status 0x%x\n", interrupt_enables); 1188 1189 if (!interrupt_enables) 1190 return IRQ_NONE; 1191 1192 spin_lock(&host->lock); 1193 1194 /* Assuming one port per host controller */ 1195 1196 ap = host->ports[0]; 1197 if (ap) { 1198 sata_fsl_host_intr(ap); 1199 } else { 1200 dev_warn(host->dev, "interrupt on disabled port 0\n"); 1201 } 1202 1203 iowrite32(interrupt_enables, hcr_base + HSTATUS); 1204 handled = 1; 1205 1206 spin_unlock(&host->lock); 1207 1208 return IRQ_RETVAL(handled); 1209} 1210 1211/* 1212 * Multiple ports are represented by multiple SATA controllers with 1213 * one port per controller 1214 */ 1215static int sata_fsl_init_controller(struct ata_host *host) 1216{ 1217 struct sata_fsl_host_priv *host_priv = host->private_data; 1218 void __iomem *hcr_base = host_priv->hcr_base; 1219 u32 temp; 1220 1221 /* 1222 * NOTE : We cannot bring the controller online before setting 1223 * the CHBA, hence main controller initialization is done as 1224 * part of the port_start() callback 1225 */ 1226 1227 /* sata controller to operate in enterprise mode */ 1228 temp = ioread32(hcr_base + HCONTROL); 1229 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); 1230 1231 /* ack. any pending IRQs for this controller/port */ 1232 temp = ioread32(hcr_base + HSTATUS); 1233 if (temp & 0x3F) 1234 iowrite32((temp & 0x3F), hcr_base + HSTATUS); 1235 1236 /* Keep interrupts disabled on the controller */ 1237 temp = ioread32(hcr_base + HCONTROL); 1238 iowrite32((temp & ~0x3F), hcr_base + HCONTROL); 1239 1240 /* Disable interrupt coalescing control(icc), for the moment */ 1241 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); 1242 iowrite32(0x01000000, hcr_base + ICC); 1243 1244 /* clear error registers, SError is cleared by libATA */ 1245 iowrite32(0x00000FFFF, hcr_base + CE); 1246 iowrite32(0x00000FFFF, hcr_base + DE); 1247 1248 /* 1249 * host controller will be brought on-line, during xx_port_start() 1250 * callback, that should also initiate the OOB, COMINIT sequence 1251 */ 1252 1253 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); 1254 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); 1255 1256 return 0; 1257} 1258 1259/* 1260 * scsi mid-layer and libata interface structures 1261 */ 1262static struct scsi_host_template sata_fsl_sht = { 1263 ATA_NCQ_SHT("sata_fsl"), 1264 .can_queue = SATA_FSL_QUEUE_DEPTH, 1265 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, 1266 .dma_boundary = ATA_DMA_BOUNDARY, 1267}; 1268 1269static struct ata_port_operations sata_fsl_ops = { 1270 .inherits = &sata_pmp_port_ops, 1271 1272 .qc_defer = ata_std_qc_defer, 1273 .qc_prep = sata_fsl_qc_prep, 1274 .qc_issue = sata_fsl_qc_issue, 1275 .qc_fill_rtf = sata_fsl_qc_fill_rtf, 1276 1277 .scr_read = sata_fsl_scr_read, 1278 .scr_write = sata_fsl_scr_write, 1279 1280 .freeze = sata_fsl_freeze, 1281 .thaw = sata_fsl_thaw, 1282 .softreset = sata_fsl_softreset, 1283 .hardreset = sata_fsl_hardreset, 1284 .pmp_softreset = sata_fsl_softreset, 1285 .error_handler = sata_fsl_error_handler, 1286 .post_internal_cmd = sata_fsl_post_internal_cmd, 1287 1288 .port_start = sata_fsl_port_start, 1289 .port_stop = sata_fsl_port_stop, 1290 1291 .pmp_attach = sata_fsl_pmp_attach, 1292 .pmp_detach = sata_fsl_pmp_detach, 1293}; 1294 1295static const struct ata_port_info sata_fsl_port_info[] = { 1296 { 1297 .flags = SATA_FSL_HOST_FLAGS, 1298 .pio_mask = ATA_PIO4, 1299 .udma_mask = ATA_UDMA6, 1300 .port_ops = &sata_fsl_ops, 1301 }, 1302}; 1303 1304static int sata_fsl_probe(struct platform_device *ofdev) 1305{ 1306 int retval = -ENXIO; 1307 void __iomem *hcr_base = NULL; 1308 void __iomem *ssr_base = NULL; 1309 void __iomem *csr_base = NULL; 1310 struct sata_fsl_host_priv *host_priv = NULL; 1311 int irq; 1312 struct ata_host *host; 1313 u32 temp; 1314 1315 struct ata_port_info pi = sata_fsl_port_info[0]; 1316 const struct ata_port_info *ppi[] = { &pi, NULL }; 1317 1318 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n"); 1319 1320 hcr_base = of_iomap(ofdev->dev.of_node, 0); 1321 if (!hcr_base) 1322 goto error_exit_with_cleanup; 1323 1324 ssr_base = hcr_base + 0x100; 1325 csr_base = hcr_base + 0x140; 1326 1327 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { 1328 temp = ioread32(csr_base + TRANSCFG); 1329 temp = temp & 0xffffffe0; 1330 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); 1331 } 1332 1333 DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); 1334 DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); 1335 DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); 1336 1337 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); 1338 if (!host_priv) 1339 goto error_exit_with_cleanup; 1340 1341 host_priv->hcr_base = hcr_base; 1342 host_priv->ssr_base = ssr_base; 1343 host_priv->csr_base = csr_base; 1344 1345 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1346 if (irq < 0) { 1347 dev_err(&ofdev->dev, "invalid irq from platform\n"); 1348 goto error_exit_with_cleanup; 1349 } 1350 host_priv->irq = irq; 1351 1352 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) 1353 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; 1354 else 1355 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; 1356 1357 /* allocate host structure */ 1358 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); 1359 1360 /* host->iomap is not used currently */ 1361 host->private_data = host_priv; 1362 1363 /* initialize host controller */ 1364 sata_fsl_init_controller(host); 1365 1366 /* 1367 * Now, register with libATA core, this will also initiate the 1368 * device discovery process, invoking our port_start() handler & 1369 * error_handler() to execute a dummy Softreset EH session 1370 */ 1371 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, 1372 &sata_fsl_sht); 1373 1374 dev_set_drvdata(&ofdev->dev, host); 1375 1376 return 0; 1377 1378error_exit_with_cleanup: 1379 1380 if (hcr_base) 1381 iounmap(hcr_base); 1382 if (host_priv) 1383 kfree(host_priv); 1384 1385 return retval; 1386} 1387 1388static int sata_fsl_remove(struct platform_device *ofdev) 1389{ 1390 struct ata_host *host = dev_get_drvdata(&ofdev->dev); 1391 struct sata_fsl_host_priv *host_priv = host->private_data; 1392 1393 ata_host_detach(host); 1394 1395 dev_set_drvdata(&ofdev->dev, NULL); 1396 1397 irq_dispose_mapping(host_priv->irq); 1398 iounmap(host_priv->hcr_base); 1399 kfree(host_priv); 1400 1401 return 0; 1402} 1403 1404#ifdef CONFIG_PM 1405static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) 1406{ 1407 struct ata_host *host = dev_get_drvdata(&op->dev); 1408 return ata_host_suspend(host, state); 1409} 1410 1411static int sata_fsl_resume(struct platform_device *op) 1412{ 1413 struct ata_host *host = dev_get_drvdata(&op->dev); 1414 struct sata_fsl_host_priv *host_priv = host->private_data; 1415 int ret; 1416 void __iomem *hcr_base = host_priv->hcr_base; 1417 struct ata_port *ap = host->ports[0]; 1418 struct sata_fsl_port_priv *pp = ap->private_data; 1419 1420 ret = sata_fsl_init_controller(host); 1421 if (ret) { 1422 dev_err(&op->dev, "Error initializing hardware\n"); 1423 return ret; 1424 } 1425 1426 /* Recovery the CHBA register in host controller cmd register set */ 1427 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); 1428 1429 iowrite32((ioread32(hcr_base + HCONTROL) 1430 | HCONTROL_ONLINE_PHY_RST 1431 | HCONTROL_SNOOP_ENABLE 1432 | HCONTROL_PMP_ATTACHED), 1433 hcr_base + HCONTROL); 1434 1435 ata_host_resume(host); 1436 return 0; 1437} 1438#endif 1439 1440static struct of_device_id fsl_sata_match[] = { 1441 { 1442 .compatible = "fsl,pq-sata", 1443 }, 1444 { 1445 .compatible = "fsl,pq-sata-v2", 1446 }, 1447 {}, 1448}; 1449 1450MODULE_DEVICE_TABLE(of, fsl_sata_match); 1451 1452static struct platform_driver fsl_sata_driver = { 1453 .driver = { 1454 .name = "fsl-sata", 1455 .owner = THIS_MODULE, 1456 .of_match_table = fsl_sata_match, 1457 }, 1458 .probe = sata_fsl_probe, 1459 .remove = sata_fsl_remove, 1460#ifdef CONFIG_PM 1461 .suspend = sata_fsl_suspend, 1462 .resume = sata_fsl_resume, 1463#endif 1464}; 1465 1466module_platform_driver(fsl_sata_driver); 1467 1468MODULE_LICENSE("GPL"); 1469MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); 1470MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); 1471MODULE_VERSION("1.10"); 1472