sata_sil.c revision 0d5ff566779f894ca9937231a181eb31e4adff0e
1/* 2 * sata_sil.c - Silicon Image SATA 3 * 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com> 5 * Please ALWAYS copy linux-ide@vger.kernel.org 6 * on emails. 7 * 8 * Copyright 2003-2005 Red Hat, Inc. 9 * Copyright 2003 Benjamin Herrenschmidt 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2, or (at your option) 15 * any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; see the file COPYING. If not, write to 24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 26 * 27 * libata documentation is available via 'make {ps|pdf}docs', 28 * as Documentation/DocBook/libata.* 29 * 30 * Documentation for SiI 3112: 31 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 32 * 33 * Other errata and documentation available under NDA. 34 * 35 */ 36 37#include <linux/kernel.h> 38#include <linux/module.h> 39#include <linux/pci.h> 40#include <linux/init.h> 41#include <linux/blkdev.h> 42#include <linux/delay.h> 43#include <linux/interrupt.h> 44#include <linux/device.h> 45#include <scsi/scsi_host.h> 46#include <linux/libata.h> 47 48#define DRV_NAME "sata_sil" 49#define DRV_VERSION "2.0" 50 51enum { 52 SIL_MMIO_BAR = 5, 53 54 /* 55 * host flags 56 */ 57 SIL_FLAG_NO_SATA_IRQ = (1 << 28), 58 SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), 59 SIL_FLAG_MOD15WRITE = (1 << 30), 60 61 SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | 62 ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME, 63 64 /* 65 * Controller IDs 66 */ 67 sil_3112 = 0, 68 sil_3112_no_sata_irq = 1, 69 sil_3512 = 2, 70 sil_3114 = 3, 71 72 /* 73 * Register offsets 74 */ 75 SIL_SYSCFG = 0x48, 76 77 /* 78 * Register bits 79 */ 80 /* SYSCFG */ 81 SIL_MASK_IDE0_INT = (1 << 22), 82 SIL_MASK_IDE1_INT = (1 << 23), 83 SIL_MASK_IDE2_INT = (1 << 24), 84 SIL_MASK_IDE3_INT = (1 << 25), 85 SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, 86 SIL_MASK_4PORT = SIL_MASK_2PORT | 87 SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, 88 89 /* BMDMA/BMDMA2 */ 90 SIL_INTR_STEERING = (1 << 1), 91 92 SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ 93 SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ 94 SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ 95 SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ 96 SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ 97 SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ 98 SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ 99 SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ 100 SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ 101 SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ 102 103 /* SIEN */ 104 SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ 105 106 /* 107 * Others 108 */ 109 SIL_QUIRK_MOD15WRITE = (1 << 0), 110 SIL_QUIRK_UDMA5MAX = (1 << 1), 111}; 112 113static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 114#ifdef CONFIG_PM 115static int sil_pci_device_resume(struct pci_dev *pdev); 116#endif 117static void sil_dev_config(struct ata_port *ap, struct ata_device *dev); 118static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg); 119static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); 120static void sil_post_set_mode (struct ata_port *ap); 121static irqreturn_t sil_interrupt(int irq, void *dev_instance); 122static void sil_freeze(struct ata_port *ap); 123static void sil_thaw(struct ata_port *ap); 124 125 126static const struct pci_device_id sil_pci_tbl[] = { 127 { PCI_VDEVICE(CMD, 0x3112), sil_3112 }, 128 { PCI_VDEVICE(CMD, 0x0240), sil_3112 }, 129 { PCI_VDEVICE(CMD, 0x3512), sil_3512 }, 130 { PCI_VDEVICE(CMD, 0x3114), sil_3114 }, 131 { PCI_VDEVICE(ATI, 0x436e), sil_3112 }, 132 { PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq }, 133 { PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq }, 134 135 { } /* terminate list */ 136}; 137 138 139/* TODO firmware versions should be added - eric */ 140static const struct sil_drivelist { 141 const char * product; 142 unsigned int quirk; 143} sil_blacklist [] = { 144 { "ST320012AS", SIL_QUIRK_MOD15WRITE }, 145 { "ST330013AS", SIL_QUIRK_MOD15WRITE }, 146 { "ST340017AS", SIL_QUIRK_MOD15WRITE }, 147 { "ST360015AS", SIL_QUIRK_MOD15WRITE }, 148 { "ST380023AS", SIL_QUIRK_MOD15WRITE }, 149 { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, 150 { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, 151 { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, 152 { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, 153 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, 154 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, 155 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, 156 { } 157}; 158 159static struct pci_driver sil_pci_driver = { 160 .name = DRV_NAME, 161 .id_table = sil_pci_tbl, 162 .probe = sil_init_one, 163 .remove = ata_pci_remove_one, 164#ifdef CONFIG_PM 165 .suspend = ata_pci_device_suspend, 166 .resume = sil_pci_device_resume, 167#endif 168}; 169 170static struct scsi_host_template sil_sht = { 171 .module = THIS_MODULE, 172 .name = DRV_NAME, 173 .ioctl = ata_scsi_ioctl, 174 .queuecommand = ata_scsi_queuecmd, 175 .can_queue = ATA_DEF_QUEUE, 176 .this_id = ATA_SHT_THIS_ID, 177 .sg_tablesize = LIBATA_MAX_PRD, 178 .cmd_per_lun = ATA_SHT_CMD_PER_LUN, 179 .emulated = ATA_SHT_EMULATED, 180 .use_clustering = ATA_SHT_USE_CLUSTERING, 181 .proc_name = DRV_NAME, 182 .dma_boundary = ATA_DMA_BOUNDARY, 183 .slave_configure = ata_scsi_slave_config, 184 .slave_destroy = ata_scsi_slave_destroy, 185 .bios_param = ata_std_bios_param, 186 .suspend = ata_scsi_device_suspend, 187 .resume = ata_scsi_device_resume, 188}; 189 190static const struct ata_port_operations sil_ops = { 191 .port_disable = ata_port_disable, 192 .dev_config = sil_dev_config, 193 .tf_load = ata_tf_load, 194 .tf_read = ata_tf_read, 195 .check_status = ata_check_status, 196 .exec_command = ata_exec_command, 197 .dev_select = ata_std_dev_select, 198 .post_set_mode = sil_post_set_mode, 199 .bmdma_setup = ata_bmdma_setup, 200 .bmdma_start = ata_bmdma_start, 201 .bmdma_stop = ata_bmdma_stop, 202 .bmdma_status = ata_bmdma_status, 203 .qc_prep = ata_qc_prep, 204 .qc_issue = ata_qc_issue_prot, 205 .data_xfer = ata_data_xfer, 206 .freeze = sil_freeze, 207 .thaw = sil_thaw, 208 .error_handler = ata_bmdma_error_handler, 209 .post_internal_cmd = ata_bmdma_post_internal_cmd, 210 .irq_handler = sil_interrupt, 211 .irq_clear = ata_bmdma_irq_clear, 212 .scr_read = sil_scr_read, 213 .scr_write = sil_scr_write, 214 .port_start = ata_port_start, 215}; 216 217static const struct ata_port_info sil_port_info[] = { 218 /* sil_3112 */ 219 { 220 .sht = &sil_sht, 221 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, 222 .pio_mask = 0x1f, /* pio0-4 */ 223 .mwdma_mask = 0x07, /* mwdma0-2 */ 224 .udma_mask = 0x3f, /* udma0-5 */ 225 .port_ops = &sil_ops, 226 }, 227 /* sil_3112_no_sata_irq */ 228 { 229 .sht = &sil_sht, 230 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | 231 SIL_FLAG_NO_SATA_IRQ, 232 .pio_mask = 0x1f, /* pio0-4 */ 233 .mwdma_mask = 0x07, /* mwdma0-2 */ 234 .udma_mask = 0x3f, /* udma0-5 */ 235 .port_ops = &sil_ops, 236 }, 237 /* sil_3512 */ 238 { 239 .sht = &sil_sht, 240 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 241 .pio_mask = 0x1f, /* pio0-4 */ 242 .mwdma_mask = 0x07, /* mwdma0-2 */ 243 .udma_mask = 0x3f, /* udma0-5 */ 244 .port_ops = &sil_ops, 245 }, 246 /* sil_3114 */ 247 { 248 .sht = &sil_sht, 249 .flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, 250 .pio_mask = 0x1f, /* pio0-4 */ 251 .mwdma_mask = 0x07, /* mwdma0-2 */ 252 .udma_mask = 0x3f, /* udma0-5 */ 253 .port_ops = &sil_ops, 254 }, 255}; 256 257/* per-port register offsets */ 258/* TODO: we can probably calculate rather than use a table */ 259static const struct { 260 unsigned long tf; /* ATA taskfile register block */ 261 unsigned long ctl; /* ATA control/altstatus register block */ 262 unsigned long bmdma; /* DMA register block */ 263 unsigned long bmdma2; /* DMA register block #2 */ 264 unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ 265 unsigned long scr; /* SATA control register block */ 266 unsigned long sien; /* SATA Interrupt Enable register */ 267 unsigned long xfer_mode;/* data transfer mode register */ 268 unsigned long sfis_cfg; /* SATA FIS reception config register */ 269} sil_port[] = { 270 /* port 0 ... */ 271 { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, 272 { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, 273 { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, 274 { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, 275 /* ... port 3 */ 276}; 277 278MODULE_AUTHOR("Jeff Garzik"); 279MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); 280MODULE_LICENSE("GPL"); 281MODULE_DEVICE_TABLE(pci, sil_pci_tbl); 282MODULE_VERSION(DRV_VERSION); 283 284static int slow_down = 0; 285module_param(slow_down, int, 0444); 286MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); 287 288 289static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) 290{ 291 u8 cache_line = 0; 292 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); 293 return cache_line; 294} 295 296static void sil_post_set_mode (struct ata_port *ap) 297{ 298 struct ata_host *host = ap->host; 299 struct ata_device *dev; 300 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 301 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; 302 u32 tmp, dev_mode[2]; 303 unsigned int i; 304 305 for (i = 0; i < 2; i++) { 306 dev = &ap->device[i]; 307 if (!ata_dev_enabled(dev)) 308 dev_mode[i] = 0; /* PIO0/1/2 */ 309 else if (dev->flags & ATA_DFLAG_PIO) 310 dev_mode[i] = 1; /* PIO3/4 */ 311 else 312 dev_mode[i] = 3; /* UDMA */ 313 /* value 2 indicates MDMA */ 314 } 315 316 tmp = readl(addr); 317 tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); 318 tmp |= dev_mode[0]; 319 tmp |= (dev_mode[1] << 4); 320 writel(tmp, addr); 321 readl(addr); /* flush */ 322} 323 324static inline void __iomem *sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) 325{ 326 void __iomem *offset = ap->ioaddr.scr_addr; 327 328 switch (sc_reg) { 329 case SCR_STATUS: 330 return offset + 4; 331 case SCR_ERROR: 332 return offset + 8; 333 case SCR_CONTROL: 334 return offset; 335 default: 336 /* do nothing */ 337 break; 338 } 339 340 return 0; 341} 342 343static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) 344{ 345 void __iomem *mmio = sil_scr_addr(ap, sc_reg); 346 if (mmio) 347 return readl(mmio); 348 return 0xffffffffU; 349} 350 351static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) 352{ 353 void __iomem *mmio = sil_scr_addr(ap, sc_reg); 354 if (mmio) 355 writel(val, mmio); 356} 357 358static void sil_host_intr(struct ata_port *ap, u32 bmdma2) 359{ 360 struct ata_eh_info *ehi = &ap->eh_info; 361 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); 362 u8 status; 363 364 if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { 365 u32 serror; 366 367 /* SIEN doesn't mask SATA IRQs on some 3112s. Those 368 * controllers continue to assert IRQ as long as 369 * SError bits are pending. Clear SError immediately. 370 */ 371 serror = sil_scr_read(ap, SCR_ERROR); 372 sil_scr_write(ap, SCR_ERROR, serror); 373 374 /* Trigger hotplug and accumulate SError only if the 375 * port isn't already frozen. Otherwise, PHY events 376 * during hardreset makes controllers with broken SIEN 377 * repeat probing needlessly. 378 */ 379 if (!(ap->pflags & ATA_PFLAG_FROZEN)) { 380 ata_ehi_hotplugged(&ap->eh_info); 381 ap->eh_info.serror |= serror; 382 } 383 384 goto freeze; 385 } 386 387 if (unlikely(!qc || qc->tf.ctl & ATA_NIEN)) 388 goto freeze; 389 390 /* Check whether we are expecting interrupt in this state */ 391 switch (ap->hsm_task_state) { 392 case HSM_ST_FIRST: 393 /* Some pre-ATAPI-4 devices assert INTRQ 394 * at this state when ready to receive CDB. 395 */ 396 397 /* Check the ATA_DFLAG_CDB_INTR flag is enough here. 398 * The flag was turned on only for atapi devices. 399 * No need to check is_atapi_taskfile(&qc->tf) again. 400 */ 401 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) 402 goto err_hsm; 403 break; 404 case HSM_ST_LAST: 405 if (qc->tf.protocol == ATA_PROT_DMA || 406 qc->tf.protocol == ATA_PROT_ATAPI_DMA) { 407 /* clear DMA-Start bit */ 408 ap->ops->bmdma_stop(qc); 409 410 if (bmdma2 & SIL_DMA_ERROR) { 411 qc->err_mask |= AC_ERR_HOST_BUS; 412 ap->hsm_task_state = HSM_ST_ERR; 413 } 414 } 415 break; 416 case HSM_ST: 417 break; 418 default: 419 goto err_hsm; 420 } 421 422 /* check main status, clearing INTRQ */ 423 status = ata_chk_status(ap); 424 if (unlikely(status & ATA_BUSY)) 425 goto err_hsm; 426 427 /* ack bmdma irq events */ 428 ata_bmdma_irq_clear(ap); 429 430 /* kick HSM in the ass */ 431 ata_hsm_move(ap, qc, status, 0); 432 433 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA || 434 qc->tf.protocol == ATA_PROT_ATAPI_DMA)) 435 ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2); 436 437 return; 438 439 err_hsm: 440 qc->err_mask |= AC_ERR_HSM; 441 freeze: 442 ata_port_freeze(ap); 443} 444 445static irqreturn_t sil_interrupt(int irq, void *dev_instance) 446{ 447 struct ata_host *host = dev_instance; 448 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; 449 int handled = 0; 450 int i; 451 452 spin_lock(&host->lock); 453 454 for (i = 0; i < host->n_ports; i++) { 455 struct ata_port *ap = host->ports[i]; 456 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); 457 458 if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) 459 continue; 460 461 /* turn off SATA_IRQ if not supported */ 462 if (ap->flags & SIL_FLAG_NO_SATA_IRQ) 463 bmdma2 &= ~SIL_DMA_SATA_IRQ; 464 465 if (bmdma2 == 0xffffffff || 466 !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) 467 continue; 468 469 sil_host_intr(ap, bmdma2); 470 handled = 1; 471 } 472 473 spin_unlock(&host->lock); 474 475 return IRQ_RETVAL(handled); 476} 477 478static void sil_freeze(struct ata_port *ap) 479{ 480 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 481 u32 tmp; 482 483 /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ 484 writel(0, mmio_base + sil_port[ap->port_no].sien); 485 486 /* plug IRQ */ 487 tmp = readl(mmio_base + SIL_SYSCFG); 488 tmp |= SIL_MASK_IDE0_INT << ap->port_no; 489 writel(tmp, mmio_base + SIL_SYSCFG); 490 readl(mmio_base + SIL_SYSCFG); /* flush */ 491} 492 493static void sil_thaw(struct ata_port *ap) 494{ 495 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; 496 u32 tmp; 497 498 /* clear IRQ */ 499 ata_chk_status(ap); 500 ata_bmdma_irq_clear(ap); 501 502 /* turn on SATA IRQ if supported */ 503 if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) 504 writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); 505 506 /* turn on IRQ */ 507 tmp = readl(mmio_base + SIL_SYSCFG); 508 tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); 509 writel(tmp, mmio_base + SIL_SYSCFG); 510} 511 512/** 513 * sil_dev_config - Apply device/host-specific errata fixups 514 * @ap: Port containing device to be examined 515 * @dev: Device to be examined 516 * 517 * After the IDENTIFY [PACKET] DEVICE step is complete, and a 518 * device is known to be present, this function is called. 519 * We apply two errata fixups which are specific to Silicon Image, 520 * a Seagate and a Maxtor fixup. 521 * 522 * For certain Seagate devices, we must limit the maximum sectors 523 * to under 8K. 524 * 525 * For certain Maxtor devices, we must not program the drive 526 * beyond udma5. 527 * 528 * Both fixups are unfairly pessimistic. As soon as I get more 529 * information on these errata, I will create a more exhaustive 530 * list, and apply the fixups to only the specific 531 * devices/hosts/firmwares that need it. 532 * 533 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted 534 * The Maxtor quirk is in the blacklist, but I'm keeping the original 535 * pessimistic fix for the following reasons... 536 * - There seems to be less info on it, only one device gleaned off the 537 * Windows driver, maybe only one is affected. More info would be greatly 538 * appreciated. 539 * - But then again UDMA5 is hardly anything to complain about 540 */ 541static void sil_dev_config(struct ata_port *ap, struct ata_device *dev) 542{ 543 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO; 544 unsigned int n, quirks = 0; 545 unsigned char model_num[ATA_ID_PROD_LEN + 1]; 546 547 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); 548 549 for (n = 0; sil_blacklist[n].product; n++) 550 if (!strcmp(sil_blacklist[n].product, model_num)) { 551 quirks = sil_blacklist[n].quirk; 552 break; 553 } 554 555 /* limit requests to 15 sectors */ 556 if (slow_down || 557 ((ap->flags & SIL_FLAG_MOD15WRITE) && 558 (quirks & SIL_QUIRK_MOD15WRITE))) { 559 if (print_info) 560 ata_dev_printk(dev, KERN_INFO, "applying Seagate " 561 "errata fix (mod15write workaround)\n"); 562 dev->max_sectors = 15; 563 return; 564 } 565 566 /* limit to udma5 */ 567 if (quirks & SIL_QUIRK_UDMA5MAX) { 568 if (print_info) 569 ata_dev_printk(dev, KERN_INFO, "applying Maxtor " 570 "errata fix %s\n", model_num); 571 dev->udma_mask &= ATA_UDMA5; 572 return; 573 } 574} 575 576static void sil_init_controller(struct pci_dev *pdev, 577 int n_ports, unsigned long port_flags, 578 void __iomem *mmio_base) 579{ 580 u8 cls; 581 u32 tmp; 582 int i; 583 584 /* Initialize FIFO PCI bus arbitration */ 585 cls = sil_get_device_cache_line(pdev); 586 if (cls) { 587 cls >>= 3; 588 cls++; /* cls = (line_size/8)+1 */ 589 for (i = 0; i < n_ports; i++) 590 writew(cls << 8 | cls, 591 mmio_base + sil_port[i].fifo_cfg); 592 } else 593 dev_printk(KERN_WARNING, &pdev->dev, 594 "cache line size not set. Driver may not function\n"); 595 596 /* Apply R_ERR on DMA activate FIS errata workaround */ 597 if (port_flags & SIL_FLAG_RERR_ON_DMA_ACT) { 598 int cnt; 599 600 for (i = 0, cnt = 0; i < n_ports; i++) { 601 tmp = readl(mmio_base + sil_port[i].sfis_cfg); 602 if ((tmp & 0x3) != 0x01) 603 continue; 604 if (!cnt) 605 dev_printk(KERN_INFO, &pdev->dev, 606 "Applying R_ERR on DMA activate " 607 "FIS errata fix\n"); 608 writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); 609 cnt++; 610 } 611 } 612 613 if (n_ports == 4) { 614 /* flip the magic "make 4 ports work" bit */ 615 tmp = readl(mmio_base + sil_port[2].bmdma); 616 if ((tmp & SIL_INTR_STEERING) == 0) 617 writel(tmp | SIL_INTR_STEERING, 618 mmio_base + sil_port[2].bmdma); 619 } 620} 621 622static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 623{ 624 static int printed_version; 625 struct device *dev = &pdev->dev; 626 struct ata_probe_ent *probe_ent; 627 void __iomem *mmio_base; 628 int rc; 629 unsigned int i; 630 631 if (!printed_version++) 632 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); 633 634 rc = pcim_enable_device(pdev); 635 if (rc) 636 return rc; 637 638 rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); 639 if (rc == -EBUSY) 640 pcim_pin_device(pdev); 641 if (rc) 642 return rc; 643 644 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); 645 if (rc) 646 return rc; 647 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); 648 if (rc) 649 return rc; 650 651 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL); 652 if (probe_ent == NULL) 653 return -ENOMEM; 654 655 INIT_LIST_HEAD(&probe_ent->node); 656 probe_ent->dev = pci_dev_to_dev(pdev); 657 probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; 658 probe_ent->sht = sil_port_info[ent->driver_data].sht; 659 probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2; 660 probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; 661 probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask; 662 probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; 663 probe_ent->irq = pdev->irq; 664 probe_ent->irq_flags = IRQF_SHARED; 665 probe_ent->port_flags = sil_port_info[ent->driver_data].flags; 666 667 probe_ent->iomap = pcim_iomap_table(pdev); 668 669 mmio_base = probe_ent->iomap[SIL_MMIO_BAR]; 670 671 for (i = 0; i < probe_ent->n_ports; i++) { 672 probe_ent->port[i].cmd_addr = mmio_base + sil_port[i].tf; 673 probe_ent->port[i].altstatus_addr = 674 probe_ent->port[i].ctl_addr = mmio_base + sil_port[i].ctl; 675 probe_ent->port[i].bmdma_addr = mmio_base + sil_port[i].bmdma; 676 probe_ent->port[i].scr_addr = mmio_base + sil_port[i].scr; 677 ata_std_ports(&probe_ent->port[i]); 678 } 679 680 sil_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags, 681 mmio_base); 682 683 pci_set_master(pdev); 684 685 if (!ata_device_add(probe_ent)) 686 return -ENODEV; 687 688 devm_kfree(dev, probe_ent); 689 return 0; 690} 691 692#ifdef CONFIG_PM 693static int sil_pci_device_resume(struct pci_dev *pdev) 694{ 695 struct ata_host *host = dev_get_drvdata(&pdev->dev); 696 int rc; 697 698 rc = ata_pci_device_do_resume(pdev); 699 if (rc) 700 return rc; 701 702 sil_init_controller(pdev, host->n_ports, host->ports[0]->flags, 703 host->iomap[SIL_MMIO_BAR]); 704 ata_host_resume(host); 705 706 return 0; 707} 708#endif 709 710static int __init sil_init(void) 711{ 712 return pci_register_driver(&sil_pci_driver); 713} 714 715static void __exit sil_exit(void) 716{ 717 pci_unregister_driver(&sil_pci_driver); 718} 719 720 721module_init(sil_init); 722module_exit(sil_exit); 723